公开(公告)号：US08886481B1

公开(公告)日：2014-11-11

申请号：US12835184

申请日：2010-07-13

申请人： Arifur Rahman ,  Michael J. Hart ,  Venkatesan Murali

发明人： Arifur Rahman ,  Michael J. Hart ,  Venkatesan Murali

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A method of reducing variation in multi-die integrated circuits can include, for each of a plurality of dies, determining at least one performance metric and selecting at least two dies for inclusion within a multi-die integrated circuit according to the at least one performance metric. Systems and devices for executing the steps of the method are also described.

摘要翻译： 减少多管芯集成电路中的变化的方法可以包括对于多个管芯中的每一个，确定至少一个性能度量并且根据至少一个性能选择至少两个管芯以包括在多管芯集成电路内 度量。 还描述了用于执行该方法的步骤的系统和设备。

公开(公告)号：US20110215465A1

公开(公告)日：2011-09-08

申请号：US12716941

申请日：2010-03-03

申请人： Arifur Rahman ,  Venkatesan Murali

发明人： Arifur Rahman ,  Venkatesan Murali

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/2902 ,  H01L2224/29187 ,  H01L2224/30181 ,  H01L2224/30183 ,  H01L2224/32137 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/83005 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/145 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

摘要： An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

摘要翻译： 集成电路（IC）将具有第一片上互连结构的第一IC芯片（芯片）和具有第二片上互连结构的第二IC芯片组合在重建的晶片基座上。 第二IC芯片与氧化物到氧化物边缘接合边缘接合到第一IC芯片。 芯片到芯片的互连结构电耦合第一IC芯片和第二IC芯片。

公开(公告)号：US09330823B1

公开(公告)日：2016-05-03

申请号：US13329832

申请日：2011-12-19

申请人： Arifur Rahman ,  Zhaoyin D. Wu ,  Namhoon Kim

发明人： Arifur Rahman ,  Zhaoyin D. Wu ,  Namhoon Kim

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01L27/08

CPC分类号： H01F5/00 ,  H01F17/0006 ,  H01F2017/0073 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

摘要： An integrated circuit structure can include an interposer having a plurality of conductive layers and a die coupled to the interposer through an internal interconnect structure. The integrated circuit structure can include an inductor implemented within at least one of the conductive layers of the interposer. The inductor can include a first terminal and a second terminal. The first terminal and the second terminal can be coupled to the internal interconnect structure.

摘要翻译： 集成电路结构可以包括具有多个导电层的插入器和通过内部互连结构耦合到插入器的管芯。 集成电路结构可以包括实现在插入器的至少一个导电层内的电感器。 电感器可以包括第一端子和第二端子。 第一端子和第二端子可以耦合到内部互连结构。

公开(公告)号：US08648615B2

公开(公告)日：2014-02-11

申请号：US12824536

申请日：2010-06-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G01R31/20

CPC分类号： G01R31/318513 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/20 ,  H01L22/22 ,  H01L22/32 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

摘要： A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

摘要翻译： 测试多芯片集成电路（IC）的方法可以包括测试多芯片IC的管芯间连接。 管芯间连接可以包括将第一管芯耦合到第二管芯的微突起。 该方法可以包括在芯片间连接的测试期间检测故障是否发生。 响应于检测故障，多芯片集成电路可以被指定为包括故障的管芯间连接。 还描述了一种集成电路，其包括第一管芯，可以设置第一管芯的第二管芯，将第一管芯耦合到第二管芯的多个管芯间连接，以及多个探针焊盘，其中每个探针 焊盘耦合到至少一个管芯间连接。

公开(公告)号：US08332803B1

公开(公告)日：2012-12-11

申请号：US12824542

申请日：2010-06-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5018 ,  G06F2217/76 ,  G06F2217/80

摘要： A method and apparatus for integrated circuit package thermo-mechanical reliability analysis are described. In some examples, a computer-implemented method of modeling stress in a packaged semiconductor device includes: selecting, using a computer, successive portions of a package layout for the semiconductor device, each of the successive portions of the package layout describing physical layout of at least one interconnect structure in the semiconductor device; for each portion of the successive portions of the package layout: (1) selecting a pre-defined layout from a library of pre-defined layouts based on the portion of the package layout; (2) obtaining pre-characterization information for the pre-defined layout that defines structural properties of the pre-defined layout; and (3) executing a modeling algorithm to determine a stress measurement for the portion of the package layout using the pre-characterization information as parametric input; and combining stress measurements for each of the successive portions of the package layout to determine a stress profile for the semiconductor device.

摘要翻译： 描述了用于集成电路封装热机械可靠性分析的方法和装置。 在一些示例中，计算机实现的封装半导体器件中的应力建模方法包括：使用计算机选择用于半导体器件的封装布局的连续部分，封装布局的每个连续部分描述物理布局 半导体器件中的至少一个互连结构; 对于包装布局的连续部分的每个部分：（1）基于包装布局的部分从预定义布局的库中选择预定义的布局; （2）获得预定义布局的预定义信息，该预定义布局定义预定义布局的结构特性; 和（3）执行建模算法以使用预表征信息作为参数输入来确定包装布局的部分的应力测量; 以及将包装布局的每个连续部分的应力测量结合以确定半导体器件的应力分布。

公开(公告)号：US08179159B1

公开(公告)日：2012-05-15

申请号：US13116276

申请日：2011-05-26

申请人： Stephen M. Trimberger ,  Arifur Rahman

发明人： Stephen M. Trimberger ,  Arifur Rahman

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17736

摘要： A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.

摘要翻译： 一种配置具有可配置逻辑的第一IC芯片的堆叠集成电路（“IC”）和通过芯片间触点阵列电耦合到第一IC裸片的第二IC裸片的方法包括：提供具有帧数据的帧和 第一IC芯片的帧头中的帧地址; 将帧数据存储在第一IC芯片的帧数据寄存器中; 处理帧头以确定帧目的地是否在第一IC管芯或第二IC管芯中; 响应于确定帧目的地在第二IC芯片中，通过包括第一多个芯片间接触阵列的片间帧地址总线将第二IC芯片提供帧地址; 以及通过包括第二多个芯片间接触阵列的片间帧数据总线将帧数据从第一IC芯片的帧数据寄存器写入帧目的地。

公开(公告)号：US07973555B1

公开(公告)日：2011-07-05

申请号：US12128459

申请日：2008-05-28

申请人： Stephen M. Trimberger ,  Arifur Rahman

发明人： Stephen M. Trimberger ,  Arifur Rahman

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： H03K19/17736

摘要： A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

摘要翻译： 半导体器件包括具有帧地址总线（604）的现场可编程门阵列（“FPGA”）管芯（202），帧数据总线（608）和第二集成电路（“IC”）芯片（204） 连接到FPGA模具。 芯片间帧地址总线（605）将至少在FPGA管芯和第二IC管芯之间的帧的帧地址的低位帧地址位耦合。 片间帧地址总线包括形成在FPGA管芯和第二IC管芯之间的第一多个触点（614）。 芯片间帧数据总线将帧的帧数据耦合在FPGA管芯和第二IC管芯之间。 芯片间帧数据总线包括形成在FPGA管芯和第二IC管芯之间的第二多个触点（616）。

公开(公告)号：US07884398B2

公开(公告)日：2011-02-08

申请号：US12328893

申请日：2008-12-05

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： H01L27/148

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US07781879B1

公开(公告)日：2010-08-24

申请号：US12503429

申请日：2009-07-15

申请人： Arifur Rahman ,  Stephen M. Trimberger

发明人： Arifur Rahman ,  Stephen M. Trimberger

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/642 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19103 ,  H01L2924/00014

摘要： Apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.

摘要翻译： 描述了用于在堆叠集成电路中集成电容器的装置。 本发明的一个方面涉及一种具有载体衬底，多个集成电路芯片和至少一种金属 - 绝缘体 - 金属（MIM）电容器的半导体组件。 集成电路芯片垂直堆叠在载体基板上。 每个MIM电容器设置在多个集成电路芯片的第一集成电路管芯和第二集成电路管芯之间。 所述至少一个MIM电容器被制造在所述第一集成电路管芯的表面和所述第二集成电路管芯的背面中的至少一个上。

公开(公告)号：US07723207B2

公开(公告)日：2010-05-25

申请号：US11737598

申请日：2007-04-19

申请人： Syed M. Alam ,  Ibrahim M. Elfadel ,  Kathryn W Guarini ,  Meikei Ieong ,  Prabhakar N. Kudva ,  David S. Kung ,  Mark A. Lavin ,  Arifur Rahman

发明人： Syed M. Alam ,  Ibrahim M. Elfadel ,  Kathryn W Guarini ,  Meikei Ieong ,  Prabhakar N. Kudva ,  David S. Kung ,  Mark A. Lavin ,  Arifur Rahman

IPC分类号： H01L21/30

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/84 ,  H01L27/1203

摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

摘要翻译： 三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。 该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。 这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。