发明授权
- 专利标题： Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process
- 专利标题（中）： 产生导电特征的偏置调整布局设计的方法和产生预定制造工艺的仿真模型的方法
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申请号： US13370994申请日： 2012-02-10
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公开(公告)号： US08887106B2公开(公告)日： 2014-11-11
- 发明人: Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
- 申请人： Chia-Ming Ho , Ke-Ying Su , Hsiao-Shu Chao , Yi-Kan Cheng
- 申请人地址： TW
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW
- 代理机构： Lowe Hauptman & Ham, LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.
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