公开(公告)号：US08887106B2

公开(公告)日：2014-11-11

申请号：US13370994

申请日：2012-02-10

申请人： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chia-Ming Ho ,  Ke-Ying Su ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5072

摘要： A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

摘要翻译： 产生导电特征的偏置调节布局设计的方法包括接收导电特征的布局设计。 如果布局设计的几何配置在预定标准的第一组内，则根据第一布局偏置规则产生导电特征的偏置调整布局设计。 如果布局设计的几何结构在预定标准的第二组内，则根据第二布局偏差规则产生导电特征的偏置调节布局设计。

公开(公告)号：US20120260225A1

公开(公告)日：2012-10-11

申请号：US13527096

申请日：2012-06-19

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

公开(公告)号：US20090007035A1

公开(公告)日：2009-01-01

申请号：US11865304

申请日：2007-10-01

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

公开(公告)号：US08214784B2

公开(公告)日：2012-07-03

申请号：US12893870

申请日：2010-09-29

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

公开(公告)号：US07181664B2

公开(公告)日：2007-02-20

申请号：US10827507

申请日：2004-04-19

申请人： Herng-Jer Lee ,  Chia-Ming Ho ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Herng-Jer Lee ,  Chia-Ming Ho ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： A method for reordering a scan chain meets given constraints and minimizes peak power dissipation. The given constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The method includes embedding a developed tool into an existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics quickly judge if the problem has corresponding feasible solutions and searching the optimal solution. Modified data from the given scan chain declaration data and the scan pattern data, which satisfy the constraints, can be obtained.

摘要翻译： 扫描链重新排序的方法满足给定约束并最大限度地降低峰值功耗。 给定的约束包括最大峰值功耗，最大扫描链长度和两个连续寄存器之间的最大距离。 该方法包括将开发的工具嵌入到用于低功率电路设计的现有VLSI设计流程中。 此外，特征快速判断问题是否具有相应的可行解决方案，并寻找最优解。 可以获得来自给定的扫描链声明数据和满足约束的扫描图形数据的修改数据。

公开(公告)号：US08572537B2

公开(公告)日：2013-10-29

申请号：US13527096

申请日：2012-06-19

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan-Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan-Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

公开(公告)号：US20050235182A1

公开(公告)日：2005-10-20

申请号：US10827507

申请日：2004-04-19

申请人： Herng-Jer Lee ,  Chia-Ming Ho ,  Chia-Chi Chu ,  Wu-Shiung Feng

发明人： Herng-Jer Lee ,  Chia-Ming Ho ,  Chia-Chi Chu ,  Wu-Shiung Feng

IPC分类号： G01R31/28 ,  G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： A method for reordering a scan chain so that the given constraints are met and the peak power dissipation is minimized and disclosed. The constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The developed tool can be embedded into the existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics are quickly judging if the problem has corresponding feasible solutions and searching the optimal solution. Given the scan chain declaration data and the scan pattern data, the modified ones, which satisfy the constraints, can be obtained.

摘要翻译： 一种用于重新排序扫描链以使得给定约束得到满足并且峰值功率耗散被最小化和公开的方法。 约束包括最大峰值功耗，最大扫描链长度和两个连续寄存器之间的最大距离。 开发的工具可以嵌入现有的VLSI设计流程，用于低功耗电路设计。 此外，特征是快速判断问题是否具有相应的可行解和搜索最优解。 给定扫描链声明数据和扫描图案数据，可以获得满足约束条件的修改的数据。

公开(公告)号：US20130174112A1

公开(公告)日：2013-07-04

申请号：US13370994

申请日：2012-02-10

申请人： Chia-Ming HO ,  Ke-Ying SU ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

发明人： Chia-Ming HO ,  Ke-Ying SU ,  Hsiao-Shu CHAO ,  Yi-Kan CHENG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5072

摘要： A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

摘要翻译： 产生导电特征的偏置调节布局设计的方法包括接收导电特征的布局设计。 如果布局设计的几何配置在预定标准的第一组内，则根据第一布局偏置规则产生导电特征的偏置调整布局设计。 如果布局设计的几何结构在预定标准的第二组内，则根据第二布局偏差规则产生导电特征的偏置调节布局设计。

公开(公告)号：US20110023003A1

公开(公告)日：2011-01-27

申请号：US12893870

申请日：2010-09-29

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

公开(公告)号：US07818698B2

公开(公告)日：2010-10-19

申请号：US11865304

申请日：2007-10-01

申请人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

发明人： Ke-Ying Su ,  Chia-Ming Ho ,  Gwan Sin Chang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

摘要翻译： 提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。 使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。 各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。 有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。