Invention Grant
- Patent Title: Non-volatile semiconductor memory with bit line hierarchy
- Patent Title (中): 具有位线层级的非易失性半导体存储器
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Application No.: US13426463Application Date: 2012-03-21
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Publication No.: US08897079B2Publication Date: 2014-11-25
- Inventor: Satoshi Torii
- Applicant: Satoshi Torii
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2011-062293 20110322
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/04 ; G11C16/34

Abstract:
Local bit lines (LBL) are respectively provided for a plurality of sectors, corresponding to each of the global bit lines (GBL). Sector select transistors connect a LBL to a GBLector select lines control the on/off state of the sector select transistors for the corresponding sectors. A plurality of word lines (WL) intersect the local bit lines. Memory cells are located at the intersections between the LBL and the WL. Each memory cell connects a source line with the corresponding LBL and includes an n-channel transistor that is turned on/off by the corresponding WL. A precharge voltage is applied to a charging line. Charging transistors connect the LBL to the charging line. A charging gate line controls the on/off state of the charging transistors.
Public/Granted literature
- US20120243335A1 NON-VOLATILE SEMICONDUCTOR MEMORY WITH BIT LINE HIERARCHY Public/Granted day:2012-09-27
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