发明授权
- 专利标题： Semiconductor chip layout
- 专利标题（中）： 半导体芯片布局
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申请号： US12846763申请日： 2010-07-29
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公开(公告)号： US08901747B2公开(公告)日： 2014-12-02
- 发明人: Michael J. Miller , Mark Baumann , Richard S. Roy
- 申请人： Michael J. Miller , Mark Baumann , Richard S. Roy
- 申请人地址： US CA Santa Clara
- 专利权人： MoSys, Inc.
- 当前专利权人： MoSys, Inc.
- 当前专利权人地址： US CA Santa Clara
- 主分类号： H01L29/40
- IPC分类号： H01L29/40 ; H01L23/50
摘要：
A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
公开/授权文献
- US20120025397A1 Semiconductor Chip Layout 公开/授权日：2012-02-02
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