发明授权
- 专利标题: Transactional cache memory system
- 专利标题(中): 事务缓存系统
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申请号: US11554672申请日: 2006-10-31
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公开(公告)号: US08924653B2公开(公告)日: 2014-12-30
- 发明人: Blaine D. Gaither , Judson E. Veazey
- 申请人: Blaine D. Gaither , Judson E. Veazey
- 申请人地址: US TX Houston
- 专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人地址: US TX Houston
- 代理机构: Setter Roche LLP
- 代理商 Kyle J. Way
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G06F12/08
摘要:
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.
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