Invention Grant
US08930638B2 Method and apparatus for supporting target-side security in a cache coherent system
有权
用于在高速缓存一致系统中支持目标侧安全性的方法和装置
- Patent Title: Method and apparatus for supporting target-side security in a cache coherent system
- Patent Title (中): 用于在高速缓存一致系统中支持目标侧安全性的方法和装置
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Application No.: US13686604Application Date: 2012-11-27
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Publication No.: US08930638B2Publication Date: 2015-01-06
- Inventor: Laurent Moll , Jean-Jacques Lecler , Philippe Boucard
- Applicant: QUALCOMM Technologies, Inc.
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Technologies, Inc.
- Current Assignee: QUALCOMM Technologies, Inc.
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F12/14 ; G06F12/06 ; G06F13/16

Abstract:
A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.
Public/Granted literature
- US20140149687A1 METHOD AND APPARATUS FOR SUPPORTING TARGET-SIDE SECURITY IN A CACHE COHERENT SYSTEM Public/Granted day:2014-05-29
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