发明授权
- 专利标题： Modeling gate transconductance in a sub-circuit transistor model
- 专利标题（中）： 在子电路晶体管模型中建模门跨导
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申请号： US13194644申请日： 2011-07-29
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公开(公告)号： US08949083B2公开(公告)日： 2015-02-03
- 发明人: Jia Feng , Zhi-Yuan Wu , Juhi Bansal , Srinath Krishnan
- 申请人： Jia Feng , Zhi-Yuan Wu , Juhi Bansal , Srinath Krishnan
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Amerson Law Firm, PLLC
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.
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