公开(公告)号：US08940608B2

公开(公告)日：2015-01-27

申请号：US13529898

申请日：2012-06-21

申请人： Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

发明人： Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/7835 ,  H01L29/7843

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供包括第一掺杂类型的第一区域，与第一区域间隔开的第一掺杂类型的第二区域的半导体衬底，位于第一掺杂类型的第一掺杂类型的漂移区域 第一区域和第二区域以及相反掺杂类型的区域。 形成覆盖漂移区域和相反掺杂类型的区域的掩模。 然后，对第一区域和第二区域进行源/漏离子注入。 掩模防止漂移区域和相反掺杂类型的区域接收源极/漏极离子注入。

公开(公告)号：US08650523B2

公开(公告)日：2014-02-11

申请号：US13471736

申请日：2012-05-15

申请人： Zhi-Yuan Wu ,  Jia Feng ,  Juhi Bansal

发明人： Zhi-Yuan Wu ,  Jia Feng ,  Juhi Bansal

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

摘要翻译： 公开了一种用于为VLSI设计提供角落实例的子电路模型的方法。 实施例包括：确定包括具有多个特征的多个子电路模型的电路设计; 以及通过处理器将所述多个子电路模型的子电路模型与拐角实例值相关联，以及所述多个子电路模型的另一个子电路模型与另一个拐角实例值相关联。 其他实施例包括由处理器根据角实例值和其他角实例值分析电路设计。

公开(公告)号：US20130311963A1

公开(公告)日：2013-11-21

申请号：US13471736

申请日：2012-05-15

申请人： Zhi-Yuan Wu ,  Jia Feng ,  Juhi Bansal

发明人： Zhi-Yuan Wu ,  Jia Feng ,  Juhi Bansal

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

摘要翻译： 公开了一种用于为VLSI设计提供角落实例的子电路模型的方法。 实施例包括：确定包括具有多个特征的多个子电路模型的电路设计; 以及通过处理器将所述多个子电路模型的子电路模型与拐角实例值相关联，以及所述多个子电路模型的另一个子电路模型与另一个拐角实例值相关联。 其他实施例包括由处理器根据角实例值和其他角实例值分析电路设计。

公开(公告)号：US20120167979A1

公开(公告)日：2012-07-05

申请号：US13341378

申请日：2011-12-30

申请人： Dung-Ching PERNG ,  Jia-Feng FANG

发明人： Dung-Ching PERNG ,  Jia-Feng FANG

IPC分类号： H01L31/0224 ,  H01L31/18

CPC分类号： H01L31/022408 ,  H01L31/0326 ,  H01L31/0392 ,  H01L31/03923 ,  H01L31/03925 ,  H01L31/03928 ,  H01L31/0749 ,  Y02E10/541 ,  Y02P70/521

摘要： The present invention provides a thin film solar cell, which comprises: a substrate; a first electrode disposed on the substrate; a barrier layer disposed on the first electrode, wherein the material of the barrier layer is a conductive material; an ohmic contacting layer disposed on the barrier layer; an absorption layer disposed on the ohmic contacting layer; a buffer layer disposed on the absorption layer; a transparent conductive layer disposed on the buffer layer; and a second electrode disposed on the transparent conductive layer. In addition, the present invention also provides a method for manufacturing the aforementioned thin film solar cell.

摘要翻译： 本发明提供一种薄膜太阳能电池，其包括：基板; 设置在所述基板上的第一电极; 设置在所述第一电极上的阻挡层，其中所述阻挡层的材料为导电材料; 设置在阻挡层上的欧姆接触层; 设置在所述欧姆接触层上的吸收层; 设置在所述吸收层上的缓冲层; 设置在缓冲层上的透明导电层; 以及设置在所述透明导电层上的第二电极。 此外，本发明还提供一种制造上述薄膜太阳能电池的方法。

公开(公告)号：US08949083B2

公开(公告)日：2015-02-03

申请号：US13194644

申请日：2011-07-29

申请人： Jia Feng ,  Zhi-Yuan Wu ,  Juhi Bansal ,  Srinath Krishnan

发明人： Jia Feng ,  Zhi-Yuan Wu ,  Juhi Bansal ,  Srinath Krishnan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

摘要翻译： 一种用于对晶体管进行建模的方法包括提供具有至少源极节点，漏极节点和栅极节点的晶体管模型，模拟使用计算装置中的晶体管模型的器件的操作，以及在栅极节点处产生偏移电压 取决于通过该装置的电流的大小。

公开(公告)号：US20130030774A1

公开(公告)日：2013-01-31

申请号：US13194644

申请日：2011-07-29

申请人： Jia Feng ,  Zhi-Yuan Wu ,  Juhi Bansal ,  Srinath Krishnan

发明人： Jia Feng ,  Zhi-Yuan Wu ,  Juhi Bansal ,  Srinath Krishnan

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036

摘要： A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

摘要翻译： 一种用于对晶体管进行建模的方法包括提供具有至少源极节点，漏极节点和栅极节点的晶体管模型，模拟使用计算装置中的晶体管模型的器件的操作，以及在栅极节点处产生偏移电压 取决于通过该装置的电流的大小。

公开(公告)号：US07749872B2

公开(公告)日：2010-07-06

申请号：US12392261

申请日：2009-02-25

申请人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

发明人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

IPC分类号： H01L21/20

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

摘要： Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location. The relatively small physical opening and/or the change in crystalline front direction may be implemented, for example, using a material that is substantially unreactive with the liquid-phase material to contain the crystalline growth.

摘要翻译： 使用液相结晶方法实现单晶生长，其涉及通常与晶格失配材料的液相晶体生长相关的缺陷的抑制。 根据一个示例性实施例，半导体器件结构包括基本单晶区域。 使用涉及促进单晶生长的缺陷抑制的方法，使诸如Ge或半导体化合物的液相材料结晶形成单晶区域。 在一些情况下，该缺陷抑制包括使用晶体生长前沿传播的相对小的物理开口来减少和/或消除缺陷。 在其他情况下，该缺陷抑制涉及相对于结晶种子位置导致结晶前沿方向的变化。 可以例如使用与液相材料基本上不反应的材料以包含结晶生长来实现相对较小的物理开口和/或晶体前端方向的变化。

公开(公告)号：US20130344669A1

公开(公告)日：2013-12-26

申请号：US13529898

申请日：2012-06-21

申请人： Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

发明人： Jia Feng ,  Kuldeep Amarnath ,  Kevin J. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/7835 ,  H01L29/7843

摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

摘要翻译： 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供包括第一掺杂类型的第一区域，与第一区域间隔开的第一掺杂类型的第二区域的半导体衬底，位于第一掺杂类型的第一掺杂类型的漂移区域 第一区域和第二区域以及相反掺杂类型的区域。 形成覆盖漂移区域和相反掺杂类型的区域的掩模。 然后，对第一区域和第二区域进行源/漏离子注入。 掩模防止漂移区域和相反掺杂类型的区域接收源极/漏极离子注入。

公开(公告)号：US20130185133A1

公开(公告)日：2013-07-18

申请号：US13350783

申请日：2012-01-15

申请人： Linda TONG ,  Stephen James McCARTHY ,  Ryan Allen JOHNS ,  Hai-Van PHAM ,  Norman CHAN ,  Amir Bashir MANJI ,  Jia Feng ,  Marc BOURGET ,  Joey PAN ,  Hwan-Joon CHOI

发明人： Linda TONG ,  Stephen James McCARTHY ,  Ryan Allen JOHNS ,  Hai-Van PHAM ,  Norman CHAN ,  Amir Bashir MANJI ,  Jia Feng ,  Marc BOURGET ,  Joey PAN ,  Hwan-Joon CHOI

IPC分类号： G06Q30/02

CPC分类号： G06Q30/0224 ,  G06Q30/0239

摘要： In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

摘要翻译： 在一个实施例中，由一个或多个计算设备执行的方法包括为一个或多个市场相关应用存储交互信息，所述交互信息针对所述一个或多个市场相关应用的每个特定应用识别与 具体应用实例; 从请求设备接收对提供符合条件的应用的列表的请求; 基于所述交互信息确定与所述请求设备相关联的一组应用; 基于与所述请求设备相关联的所述应用集合的所述确定，向所述请求设备发送一个或多个所选择的合格应用的列表。

公开(公告)号：US20090176353A1

公开(公告)日：2009-07-09

申请号：US12392261

申请日：2009-02-25

申请人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

发明人： James D. Plummer ,  Peter B. Griffin ,  Jia Feng ,  Shu-Lu Chen

IPC分类号： H01L21/208 ,  H01L21/20

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

摘要： Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location. The relatively small physical opening and/or the change in crystalline front direction may be implemented, for example, using a material that is substantially unreactive with the liquid-phase material to contain the crystalline growth.

摘要翻译： 使用液相结晶方法实现单晶生长，其涉及通常与晶格失配材料的液相晶体生长相关的缺陷的抑制。 根据一个示例性实施例，半导体器件结构包括基本单晶区域。 使用涉及促进单晶生长的缺陷抑制的方法，使诸如Ge或半导体化合物的液相材料结晶形成单晶区域。 在一些情况下，该缺陷抑制包括使用晶体生长前沿传播的相对小的物理开口来减少和/或消除缺陷。 在其他情况下，该缺陷抑制涉及相对于结晶种子位置导致结晶前沿方向的变化。 可以例如使用与液相材料基本上不反应的材料以包含结晶生长来实现相对较小的物理开口和/或晶体前端方向的变化。