- Patent Title: High linearity SOI wafer for low-distortion circuit applications
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Application No.: US13929955Application Date: 2013-06-28
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Publication No.: US08951896B2Publication Date: 2015-02-10
- Inventor: Alan B. Botula , Jeffrey E. Hanrahan , Mark D. Jaffe , Alvin J. Joseph , Dale W. Martin , Gerd Pfeiffer , James A. Slinkman
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb & Riley, LLC
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/46 ; H01L21/04

Abstract:
According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.
Public/Granted literature
- US20150004778A1 HIGH LINEARITY SOI WAFER FOR LOW-DISTORTION CIRCUIT APPLICATIONS Public/Granted day:2015-01-01
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