A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.