发明授权
- 专利标题: Tiling compaction in multi-processor systems
- 专利标题(中): 多处理器系统中的平铺压实
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申请号: US12879582申请日: 2010-09-10
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公开(公告)号: US08963931B2公开(公告)日: 2015-02-24
- 发明人: Mark Fowler
- 申请人: Mark Fowler
- 申请人地址: US CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Volpe and Koenig, P.C.
- 主分类号: G06F15/16
- IPC分类号: G06F15/16 ; G06F15/80 ; G06F9/50 ; G06F12/02
摘要:
A method and system for processing a graphics frame in a multi-processor computing environment are described. Embodiments of the present invention enable the reduction of the memory footprint required for processing a graphics frame in a multi-processor system. In one embodiment a method of processing a graphics frame using a plurality of processors is presented. The method includes determining a respective assignment of tiles of the graphics frame to each processor of the plurality of processors; allocating a memory area in a local memory of each processor, where the size of the allocated memory area substantially corresponds to the aggregate size of tiles assigned to the respective processor; and storing the tiles of the respective assignment of tiles in the memory area of each respective processor.
公开/授权文献
- US20110057935A1 Tiling Compaction in Multi-Processor Systems 公开/授权日:2011-03-10
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