Invention Grant
- Patent Title: Gate stacks including TaXSiYO for MOSFETS
- Patent Title (中): 栅极堆叠包括用于MOSFET的TaXSiYO
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Application No.: US14135381Application Date: 2013-12-19
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Publication No.: US08975706B2Publication Date: 2015-03-10
- Inventor: Khaled Ahmed , Frank Greer
- Applicant: Intermolecular, Inc.
- Applicant Address: US CA San Jose
- Assignee: Intermolecular, Inc.
- Current Assignee: Intermolecular, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L27/092

Abstract:
Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.
Public/Granted literature
- US20150041912A1 Gate Stacks Including TaXSiYO for MOSFETS Public/Granted day:2015-02-12
Information query
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