Invention Grant
- Patent Title: Integrating through substrate vias into middle-of-line layers of integrated circuits
- Patent Title (中): 通过衬底通孔集成到集成电路的中间线层
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Application No.: US13724038Application Date: 2012-12-21
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Publication No.: US08975729B2Publication Date: 2015-03-10
- Inventor: Vidhya Ramachandran , Shiqun Gu
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle S. Gallardo
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L21/768 ; H01L23/48 ; H01L23/522
Abstract:
A semiconductor wafer has an integrated through substrate via (TSV). The semiconductor wafer includes a substrate. A dielectric layer may be formed on a first side of the substrate. A through substrate via may extend through the dielectric layer and the substrate. The through substrate via may include a conductive material and an isolation layer. The isolation layer may at least partially surround the conductive material. The isolation layer may have a tapered portion.
Public/Granted literature
- US20130181330A1 INTEGRATING THROUGH SUBSTRATE VIAS INTO MIDDLE-OF-LINE LAYERS OF INTEGRATED CIRCUITS Public/Granted day:2013-07-18
Information query
IPC分类:
