公开(公告)号：US09922970B2

公开(公告)日：2018-03-20

申请号：US14622273

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Miguel Angel Miranda Corbalan

IPC: H01L27/06 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L27/02 ,  H01L49/02 ,  H01L29/66 ,  H01L29/861

CPC classification number: H01L27/0688 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49844 ,  H01L23/5383 ,  H01L23/5389 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0676 ,  H01L28/40 ,  H01L29/6609 ,  H01L29/861

Abstract: An apparatus includes a substrate and an interposer associated with the substrate. The apparatus further includes a first device disposed within the substrate or within the interposer and a second device disposed within the interposer. The first device and the second device are arranged in a stacked configuration.

公开(公告)号：US09379201B2

公开(公告)日：2016-06-28

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L21/4763 ,  H01L29/66 ,  H01L23/498 ,  H01L29/861 ,  H01L21/768 ,  H01L29/872 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/304 ,  H01L23/48 ,  H01L23/60 ,  H01L27/02 ,  H01L27/06 ,  H01L23/535 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US09355904B2

公开(公告)日：2016-05-31

申请号：US14311405

申请日：2014-06-23

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Shiqun Gu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.

Abstract translation: 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 用于TSV应变消除的方法包括在衬底中限定通孔的通孔。 该方法还包括在空腔中沉积隔离层。 该方法还包括用导电材料填充空腔。 该方法还包括去除隔离层的一部分以形成凹陷部分。

公开(公告)号：US09276199B2

公开(公告)日：2016-03-01

申请号：US14499027

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

IPC: H01L23/552 ,  H01L43/12 ,  H01L43/02 ,  H01L23/64 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1435 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

公开(公告)号：US08952504B2

公开(公告)日：2015-02-10

申请号：US13777475

申请日：2013-02-26

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

IPC: H01L23/552 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1435 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract translation: 一些实施方案提供了包括包括几个MRAM单元的磁阻随机存取存储器（MRAM）单元阵列的管芯。 芯片还包括位于MRAM单元阵列上方的第一铁磁层，位于MRAM单元阵列下方的第二铁磁层和位于至少一个MRAM单元周围的几个通孔。 通孔包括铁磁材料。 在一些实施方案中，第一铁磁层，第二铁磁层和几个通孔限定用于MRAM单元阵列的磁屏蔽。 MRAM单元可以包括磁性隧道结（MTJ）。 在一些实施方案中，几个通孔至少穿过管芯的金属层和电介质层。 在一些实施方案中，通孔通过衬底通孔。 在一些实施方案中，铁磁材料具有高磁导率和高B饱和度。

公开(公告)号：US09941156B2

公开(公告)日：2018-04-10

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

公开(公告)号：US20160293475A1

公开(公告)日：2016-10-06

申请号：US14676728

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Vidhya Ramachandran ,  Christine Sung-An Hau-Riege ,  John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Jihong Choi ,  Jun Chen ,  Choh Fei Yeap

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract translation: 公开了减小寄生电容的装置和方法。 器件可以包括电介质层。 该器件可以包括第一和第二导电结构以及靠近电介质层的蚀刻停止层。 蚀刻停止层可以限定靠近第一和第二导电结构之间的电介质层的区域的第一和第二开口。 该装置可以包括区域内的第一和第二气隙。 该装置可以包括靠近蚀刻停止层（例如，在上方，上方或上方）的材料层。 靠近蚀刻停止层的材料层可以覆盖第一和第二气隙。

公开(公告)号：US20160049340A1

公开(公告)日：2016-02-18

申请号：US14460805

申请日：2014-08-15

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran ,  Urmi Ray

IPC: H01L21/66 ,  H01L23/48 ,  G01B7/16 ,  H01L23/00

CPC classification number: H01L22/14 ,  G01B7/16 ,  G01B2210/56 ,  H01L22/34 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/562 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/16227 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81908 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0549 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/384

Abstract: In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data.

Abstract translation: 在特定实施例中，一种装置包括位于半导体器件的第一侧上的应力传感器。 该装置还包括位于半导体器件的第二侧上的电路。 应力传感器被配置为检测半导体器件处的应力。 在另一个具体实施例中，一种方法包括从位于封装半导体器件的第一侧上的应力传感器接收数据。 封装的半导体器件包括位于封装的半导体器件的第二侧上的电路。 数据表示应力传感器检测到的应力。 该方法还包括基于该数据执行与封装半导体器件相关联的测试。

公开(公告)号：US20150333053A1

公开(公告)日：2015-11-19

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L27/02 ,  H01L23/48 ,  H01L29/66 ,  H01L21/304 ,  H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/768 ,  H01L29/872

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US20140266286A1

公开(公告)日：2014-09-18

申请号：US13801009

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vidhya Ramachandran ,  Shiqun Gu ,  Brian M. Henderson ,  Michael Scott DiBattista ,  Babak Motamedi ,  George F. Gaut

IPC: H01L23/522 ,  H01L23/525 ,  G01R31/26 ,  G06F17/50

CPC classification number: H01L23/5256 ,  G01R31/026 ,  G01R31/2884 ,  G06F17/5068 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a conductive via to provide an electrical path through a substrate. The device further includes a conductive element. The device further includes a fuse coupled to the conductive via and coupled to the conductive element to provide a conductive path between the conductive via and the conductive element. The conductive path enables testing of continuity of at least a portion of the conductive via. The fuse is configured to be disabled after the testing of the continuity of the conductive via.

Abstract translation: 一种器件包括导电通孔以提供通过衬底的电路径。 该装置还包括导电元件。 该器件还包括耦合到导电通孔并且耦合到导电元件的熔丝，以在导电通孔和导电元件之间提供导电路径。 导电路径使得能够测试导电通孔的至少一部分的连续性。 保险丝被配置为在测试导电通孔的连续性后禁用。