Invention Grant
US08975929B2 High voltage tolerant input buffer 有权
高耐压输入缓冲器

High voltage tolerant input buffer
Abstract:
A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.
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