发明授权
- 专利标题: Memory architecture optimized for random access
- 专利标题(中): 针对随机访问优化的内存架构
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申请号: US13486693申请日: 2012-06-01
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公开(公告)号: US08977930B1公开(公告)日: 2015-03-10
- 发明人: Steven Mark Casselman
- 申请人: Steven Mark Casselman
- 申请人地址: US CA Santa Clara
- 专利权人: DRC Computer Corporation
- 当前专利权人: DRC Computer Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: The Webostad Firm
- 主分类号: G11C29/00
- IPC分类号: G11C29/00 ; G06F12/08
摘要:
In an embodiment, a plurality of memory dies is coupled as a memory block. The memory block has an access width defined as a system word length divided by a burst length associated with the plurality of memory dies. The burst length is greater than one. A single word having the system word length is written or read in a write operation or a read operation, respectively, through a write burst or a read burst, respectively, for random access memory operation with a granularity of the single word.
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