发明授权
US08977930B1 Memory architecture optimized for random access 有权
针对随机访问优化的内存架构

Memory architecture optimized for random access
摘要:
In an embodiment, a plurality of memory dies is coupled as a memory block. The memory block has an access width defined as a system word length divided by a burst length associated with the plurality of memory dies. The burst length is greater than one. A single word having the system word length is written or read in a write operation or a read operation, respectively, through a write burst or a read burst, respectively, for random access memory operation with a granularity of the single word.
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