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    Compiler and Language for Parallel and Pipelined Computation
    3.
    发明申请
    Compiler and Language for Parallel and Pipelined Computation 审中-公开
    并行和流水线计算的编译器和语言

    公开(公告)号：US20140258995A1

    公开(公告)日：2014-09-11

    申请号：US14198472

    申请日：2014-03-05

    申请人： Steven Mark CASSELMAN

    发明人： Steven Mark CASSELMAN

    IPC分类号： G06F9/45

    CPC分类号： G06F8/314

    摘要： A compiler and language using the comma as a parallelism operator may ensure that variables on the left hand side of a line of code are only used once, and that the variables on the left hand side of the line of code are not being used as function arguments. Commas may be replaced with semi-colons.

    摘要翻译： 使用逗号作为并行运算符的编译器和语言可以确保代码行左侧的变量仅使用一次，并且代码行左侧的变量不被用作函数 争论 逗号可以用分号代替。

    FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
    5.
    发明授权
    FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions 失效
    FPGA虚拟计算机，用于通过响应于这些指令连续重新配置一组FPGA来执行程序指令序列

    公开(公告)号：US5684980A

    公开(公告)日：1997-11-04

    申请号：US685158

    申请日：1996-07-23

    申请人： Steven Mark Casselman

    发明人： Steven Mark Casselman

    IPC分类号： G06F9/318 ,  G06F15/78 ,  G06F17/50 ,  G06F19/00

    CPC分类号： G06F9/30181 ,  G06F15/7867 ,  G06F17/5054

    摘要： An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed. Preferably, this processor-like device is itself a "control" array of interconnected FPGAs which have been configured to emulate a selected microprocessor architecture which accepts user-defined primitives corresponding to an algorithm to be performed or a logic architecture to be emulated and reconfigure the FPGAs and the FPINs accordingly.

    摘要翻译： 一系列FPGA在执行连续的用户定义算法期间连续改变其配置。 相邻的FPGA通过外部现场可编程互连设备（FPIN）或交叉开关进行连接。 该阵列包括能够执行根据要执行的下一个算法重新配置阵列中的FPGA所必需的计算的类似处理器的设备。 优选地，该类似处理器的设备本身是互连FPGA的“控制”阵列，其被配置为模拟选择的微处理器架构，其接受与要执行的算法对应的用户定义的基元或要仿真的逻辑架构，并重新配置 FPGA和FPIN相应。

    Memory architecture optimized for random access
    6.
    发明授权
    Memory architecture optimized for random access 有权
    针对随机访问优化的内存架构

    公开(公告)号：US08977930B1

    公开(公告)日：2015-03-10

    申请号：US13486693

    申请日：2012-06-01

    申请人： Steven Mark Casselman

    发明人： Steven Mark Casselman

    IPC分类号： G11C29/00 ,  G06F12/08

    CPC分类号： G06F12/0802 ,  G06F12/0879 ,  G06F13/385 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    摘要： In an embodiment, a plurality of memory dies is coupled as a memory block. The memory block has an access width defined as a system word length divided by a burst length associated with the plurality of memory dies. The burst length is greater than one. A single word having the system word length is written or read in a write operation or a read operation, respectively, through a write burst or a read burst, respectively, for random access memory operation with a granularity of the single word.

    摘要翻译： 在一个实施例中，多个存储器管芯作为存储器块耦合。 存储器块具有被定义为系统字长度除以与多个存储器管芯相关联的突发长度的访问宽度。 突发长度大于1。 具有系统字长的单个字分别通过写突发或读脉冲分别以写入操作或读取操作的形式写入或读取，用于具有单个字的粒度的随机存取存储器操作。

    Reconfiguration of an accelerator module having a programmable logic device
    7.
    发明授权
    Reconfiguration of an accelerator module having a programmable logic device 有权
    具有可编程逻辑器件的加速器模块的重新配置

    公开(公告)号：US08145894B1

    公开(公告)日：2012-03-27

    申请号：US12392038

    申请日：2009-02-24

    申请人： Steven Mark Casselman

    发明人： Steven Mark Casselman

    IPC分类号： G06F15/177

    CPC分类号： G06F15/7871

    摘要： Reconfiguration of an accelerator module having a programmable logic device is described, where the reconfiguration is performed during runtime without rebooting. For example, a computer is put into a sleep mode, the computer having the accelerator module installed therein. A programmable logic device of the accelerator module is reconfigured while the computer is in the sleep mode.

    摘要翻译： 描述具有可编程逻辑设备的加速器模块的重新配置，其中在运行时期间执行重新配置而不重新启动。 例如，将计算机置于睡眠模式，其中安装有加速器模块的计算机。 当计算机处于睡眠模式时，重新配置加速器模块的可编程逻辑器件。