Invention Grant
US08981463B2 Memory cell array with semiconductor selection device for multiple memory cells
有权
具有多个存储单元的半导体选择装置的存储单元阵列
- Patent Title: Memory cell array with semiconductor selection device for multiple memory cells
- Patent Title (中): 具有多个存储单元的半导体选择装置的存储单元阵列
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Application No.: US14105271Application Date: 2013-12-13
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Publication No.: US08981463B2Publication Date: 2015-03-17
- Inventor: Gurtej Sandhu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dickstein Shapiro LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/06 ; H01L27/102 ; H01L27/24 ; H01L29/88 ; H01L27/088
Abstract:
A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.
Public/Granted literature
- US20140097503A1 MEMORY CELL ARRAY WITH SEMICONDUCTOR SELECTION DEVICE FOR MULTIPLE MEMORY CELLS Public/Granted day:2014-04-10
Information query
IPC分类:
