Invention Grant
- Patent Title: Balanced stress assembly for semiconductor devices
- Patent Title (中): 用于半导体器件的平衡应力组件
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Application No.: US13789722Application Date: 2013-03-08
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Publication No.: US08987875B2Publication Date: 2015-03-24
- Inventor: Carl W. Berlin , Gary L. Eesley
- Applicant: Delphi Technologies, Inc.
- Applicant Address: US MI Troy
- Assignee: Delphi Technologies, Inc.
- Current Assignee: Delphi Technologies, Inc.
- Current Assignee Address: US MI Troy
- Agent Lawrence D. Hazelton
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/00 ; H05K7/00 ; H05K3/30 ; H01L23/00 ; H01L23/498 ; H01L23/373

Abstract:
An assembly for packaging one or more electronic devices in die form. The assembly includes substrates on opposite sides of the assembly, with lead frames between the electronic devices and the substrates. The substrates, lead frames, and electronic devices are sintered together using silver-based sintering paste between each layer. The material and thicknesses of the substrates and lead frames are selected so stress experienced by the electronic devices caused by changes in temperature of the assembly are balanced from the center of the assembly, thereby eliminating the need for balancing stresses at a substrate level by applying substantially matching metal layers to both sides of the substrates.
Public/Granted literature
- US20140252578A1 BALANCED STRESS ASSEMBLY FOR SEMICONDUCTOR DEVICES Public/Granted day:2014-09-11
Information query
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