A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes with respect to a view pertaining to the aforesaid abstract (A) and applying it to the aforesaid substrate (SBS); and extracting (400), on the basis of the aforesaid subdivision grid (TG), a full electrical netlist (NC) pertaining to the substrate (SBS). The method further includes performing an evaluation (500, 600) of the interactions between devices (DV) of the electronic circuit at the substrate level according to the aforesaid full electrical netlist (NC) pertaining to the substrate (SBS).