公开(公告)号：US20140173542A1

公开(公告)日：2014-06-19

申请号：US14108462

申请日：2013-12-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giancarlo Zinco ,  Mattia Monetti

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5018 ,  G06F17/5036 ,  G06F17/5072

Abstract: A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes with respect to a view pertaining to the aforesaid abstract (A) and applying it to the aforesaid substrate (SBS); and extracting (400), on the basis of the aforesaid subdivision grid (TG), a full electrical netlist (NC) pertaining to the substrate (SBS). The method further includes performing an evaluation (500, 600) of the interactions between devices (DV) of the electronic circuit at the substrate level according to the aforesaid full electrical netlist (NC) pertaining to the substrate (SBS).

Abstract translation: 一种用于电子电路自动设计的方法，包括：产生（100）上述电子电路的布局（L）; 在与所述电子电路的布局（L）相关联的衬底水平处产生（200）抽象数据（A）; 相对于上述摘要（A）的视图生成（300）细分为网格和节点的网格（TG）并将其应用于上述基底（SBS）; 以及基于所述细分网格（TG）提取与所述基板（SBS）相关的全电网表（NC）（400）。 该方法还包括根据与衬底（SBS）相关的上述全电网表（NC），在衬底级别执行电子电路的设备（DV）之间的交互的评估（500,600）。

公开(公告)号：US20150020040A1

公开(公告)日：2015-01-15

申请号：US14325088

申请日：2014-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Mattia Monetti ,  Alberto Balzarotti

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/80

Abstract: A method for the automatic design of an electronic circuit includes operations for evaluation of the thermal effects in the electronic circuit. The method generates a layout of the electronic circuit. Abstract data at the substrate level associated to the layout of the electronic circuit is then generated. A grid of partitioning is generated with respect to a view regarding the aforesaid abstract into meshes and nodes. The grid is applied to the substrate. On the basis of the grid (TG), a list of nodes or netlist representing a thermal network that represents the thermal behavior of the substrate or of its portions or elements is extracted. The netlist is useful in simulation operations, in particular of a SPICE type, for making an evaluation of thermal effects in the electronic circuit.

Abstract translation: 电子电路的自动设计方法包括用于评估电子电路中的热效应的操作。 该方法生成电子电路的布局。 然后生成与电子电路的布局相关联的基板级的抽象数据。 相对于关于上述抽象到网格和节点的视图产生划分网格。 栅格被施加到基板上。 基于网格（TG），提取表示表示基板或其部分或元件的热行为的热网络的节点或网表的列表。 网表在仿真操作中尤其是SPICE类型有用，用于评估电子电路中的热效应。

公开(公告)号：US09384315B2

公开(公告)日：2016-07-05

申请号：US14325088

申请日：2014-07-07

Applicant: STMicroelectronics S.r.l.

Inventor： Mattia Monetti ,  Alberto Balzarotti

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/78 ,  G06F2217/80

Abstract: A method for the automatic design of an electronic circuit includes operations for evaluation of the thermal effects in the electronic circuit. The method generates a layout of the electronic circuit. Abstract data at the substrate level associated to the layout of the electronic circuit is then generated. A grid of partitioning is generated with respect to a view regarding the aforesaid abstract into meshes and nodes. The grid is applied to the substrate. On the basis of the grid (TG), a list of nodes or netlist representing a thermal network that represents the thermal behavior of the substrate or of its portions or elements is extracted. The netlist is useful in simulation operations, in particular of a SPICE type, for making an evaluation of thermal effects in the electronic circuit.

Abstract translation: 电子电路的自动设计方法包括用于评估电子电路中的热效应的操作。 该方法生成电子电路的布局。 然后生成与电子电路的布局相关联的基板级的抽象数据。 相对于关于上述抽象到网格和节点的视图产生划分网格。 栅格被施加到基板上。 基于网格（TG），提取表示表示基板或其部分或元件的热行为的热网络的节点或网表的列表。 网表在仿真操作中尤其是SPICE类型有用，用于评估电子电路中的热效应。

公开(公告)号：US08990752B2

公开(公告)日：2015-03-24

申请号：US14108462

申请日：2013-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Giancarlo Zinco ,  Mattia Monetti

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5018 ,  G06F17/5036 ,  G06F17/5072

Abstract: A method for automatic design of an electronic circuit, includes: generating (100) a layout (L) of the aforesaid electronic circuit; generating (200) abstract data (A) at the substrate level associated to the layout (L) of the aforesaid electronic circuit; generating (300) a grid (TG) of subdivision into meshes and nodes with respect to a view pertaining to the aforesaid abstract (A) and applying it to the aforesaid substrate (SBS); and extracting (400), on the basis of the aforesaid subdivision grid (TG), a full electrical netlist (NC) pertaining to the substrate (SBS). The method further includes performing an evaluation (500, 600) of the interactions between devices (DV) of the electronic circuit at the substrate level according to the aforesaid full electrical netlist (NC) pertaining to the substrate (SBS).

Abstract translation: 一种用于电子电路自动设计的方法，包括：产生（100）上述电子电路的布局（L）; 在与所述电子电路的布局（L）相关联的衬底水平处产生（200）抽象数据（A）; 相对于上述摘要（A）的视图生成（300）细分为网格和节点的网格（TG）并将其应用于上述基底（SBS）; 以及基于所述细分网格（TG）提取与所述基板（SBS）有关的全电网表（NC）（400）。 该方法还包括根据与衬底（SBS）相关的上述全电网表（NC），在衬底级别执行电子电路的设备（DV）之间的交互的评估（500,600）。