Invention Grant
US08994185B2 Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP 有权
用于3-D Fo-WLCSP的导电微孔阵列的垂直互连结构的半导体器件和方法

Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
Abstract:
A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.
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