发明授权
US09000799B1 Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces
有权
在移动接口上电排序期间实现真正的故障安全性和超低引脚电流的方法
- 专利标题： Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces
- 专利标题（中）： 在移动接口上电排序期间实现真正的故障安全性和超低引脚电流的方法
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申请号： US14043565申请日： 2013-10-01
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公开(公告)号： US09000799B1公开(公告)日： 2015-04-07
- 发明人: Devraj Matharampallil Rajagopal , Rajagopalan P
- 申请人： Texas Instruments Incorporated
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 John R. Pessetto; Frank D. Cimino
- 主分类号： H03K19/007
- IPC分类号： H03K19/007 ; H03K19/0185
摘要：
An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.
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