公开(公告)号：US10673436B1

公开(公告)日：2020-06-02

申请号：US16538513

申请日：2019-08-12

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Bharat Gajanan Hegde ,  Devraj Matharampallil Rajagopal ,  Srikanth Srinivasan

IPC分类号： H03K19/007 ,  H03K17/0814 ,  H03K3/3562 ,  H03K19/17788

摘要： A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

公开(公告)号：US11789071B2

公开(公告)日：2023-10-17

申请号：US17321470

申请日：2021-05-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Devraj Matharampallil Rajagopal ,  Nitesh Mishra

IPC分类号： G01R31/317 ,  G01R31/3177 ,  H01L21/78 ,  H01L21/66

CPC分类号： G01R31/31727 ,  G01R31/3177 ,  H01L21/78 ,  H01L22/20

摘要： An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.

公开(公告)号：US09000799B1

公开(公告)日：2015-04-07

申请号：US14043565

申请日：2013-10-01

申请人： Texas Instruments Incorporated

发明人： Devraj Matharampallil Rajagopal ,  Rajagopalan P

IPC分类号： H03K19/007 ,  H03K19/0185

CPC分类号： H03K19/007 ,  H03K19/018521

摘要： An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe circuit receives a PAD voltage. The failsafe circuit and the supply detector cell controls a leakage current from the PAD based on the IO supply voltage and the PAD voltage.

摘要翻译： 由输入/输出（IO）电源电压供电的输入/输出（IO）电路。 IO电路包括检测核心电源电压并产生电源检测信号的电源检测器单元。 驱动电路连接到PAD，驱动电路接收电源检测信号。 故障保护电路接收PAD电压。 故障保护电路和电源检测器单元根据IO电源电压和PAD电压控制来自PAD的漏电流。

公开(公告)号：US20220221512A1

公开(公告)日：2022-07-14

申请号：US17321470

申请日：2021-05-16

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Devraj Matharampallil Rajagopal ,  Nitesh Mishra

IPC分类号： G01R31/317 ,  H01L21/66 ,  H01L21/78 ,  G01R31/3177

摘要： An integrated circuit. The integrated circuit includes: (i) a clocked circuit operable in response to a clock; (ii) a clock providing circuit, coupled to clock the clocked circuit at a selectable frequency; (iii) a test circuit coupled to the clock providing circuit and the clocked circuit; and (iv) a pad configured to receive an external signal, wherein the selectable frequency is selected in response to the external signal.

公开(公告)号：US20150091616A1

公开(公告)日：2015-04-02

申请号：US14043535

申请日：2013-10-01

申请人： Texas Instruments Incorporated

发明人： Samiran Dasgupta ,  Devraj Matharampallil Rajagopal

IPC分类号： H03K19/018

CPC分类号： H03K19/01818 ,  H03K19/017518

摘要： An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.

摘要翻译： 在低电压BiCMOS工艺中能够进行高电压信号的IO电路。 IO电路包括电压轨发生器电路，其接收参考电压并产生电压轨电源。 BJT（双极结晶体管）缓冲电路耦合到电压轨发生器电路和焊盘。 BJT缓冲电路包括一个上拉电路和一个下拉电路。 上拉电路接收电压轨。 下拉电路耦合到上拉电路。 该焊盘耦合到上拉电路和下拉电路。

公开(公告)号：US11558044B2

公开(公告)日：2023-01-17

申请号：US16950245

申请日：2020-11-17

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Jhankar Malakar ,  Srikanth Srinivasan ,  Devraj Matharampallil Rajagopal

IPC分类号： H03K5/1252 ,  H03K17/687 ,  H03K17/0416 ,  H03K5/00

摘要： An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

公开(公告)号：US09054695B2

公开(公告)日：2015-06-09

申请号：US14043535

申请日：2013-10-01

申请人： Texas Instruments Incorporated

发明人： Samiran Dasgupta ,  Devraj Matharampallil Rajagopal

IPC分类号： H03K19/0175 ,  H03K19/018

CPC分类号： H03K19/01818 ,  H03K19/017518

摘要： An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.

摘要翻译： 在低电压BiCMOS工艺中能够进行高电压信号的IO电路。 IO电路包括电压轨发生器电路，其接收参考电压并产生电压轨电源。 BJT（双极结晶体管）缓冲电路耦合到电压轨发生器电路和焊盘。 BJT缓冲电路包括一个上拉电路和一个下拉电路。 上拉电路接收电压轨。 下拉电路耦合到上拉电路。 该焊盘耦合到上拉电路和下拉电路。