Invention Grant
- Patent Title: Probing chips during package formation
- Patent Title (中): 在封装形成期间探测芯片
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Application No.: US13429054Application Date: 2012-03-23
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Publication No.: US09006004B2Publication Date: 2015-04-14
- Inventor: Jing-Cheng Lin , Szu Wei Lu
- Applicant: Jing-Cheng Lin , Szu Wei Lu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/683 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; H01L21/56
Abstract:
A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.
Public/Granted literature
- US20130249532A1 Probing Chips during Package Formation Public/Granted day:2013-09-26
Information query
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