In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.