Invention Grant
US09018059B2 Memory devices having reduced interference between floating gates and methods of fabricating such devices
有权
具有降低浮动栅极之间的干扰的存储器件和制造这种器件的方法
- Patent Title: Memory devices having reduced interference between floating gates and methods of fabricating such devices
- Patent Title (中): 具有降低浮动栅极之间的干扰的存储器件和制造这种器件的方法
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Application No.: US13866698Application Date: 2013-04-19
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Publication No.: US09018059B2Publication Date: 2015-04-28
- Inventor: Seiichi Aritome
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/762 ; H01L27/115
Abstract:
A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.
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