公开(公告)号：US08897078B2

公开(公告)日：2014-11-25

申请号：US13915255

申请日：2013-06-11

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are described.

Abstract translation: 各种实施例包括用于读取电子设备中的存储器阵列的相邻单元的方法，装置和系统，以确定相邻单元的阈值电压值，相邻单元与目标单元相邻，以及读取存储器的目标单元 阵列使用基于相邻单元的阈值电压值的字线电压值。 描述了附加装置，系统和方法。

公开(公告)号：US20130193505A1

公开(公告)日：2013-08-01

申请号：US13786889

申请日：2013-03-06

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L27/105

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US10109351B2

公开(公告)日：2018-10-23

申请号：US15341410

申请日：2016-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiichi Aritome

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a program pulse width. A trim setting may be assigned to a portion of the memory device based on a program speed of the portion of the memory device.

公开(公告)号：US08729621B2

公开(公告)日：2014-05-20

申请号：US14048151

申请日：2013-10-08

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L27/108

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20140035021A1

公开(公告)日：2014-02-06

申请号：US14048151

申请日：2013-10-08

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L29/66 ,  H01L21/22 ,  H01L21/265 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20130272064A1

公开(公告)日：2013-10-17

申请号：US13915255

申请日：2013-06-11

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are described.

Abstract translation: 各种实施例包括用于读取电子设备中的存储器阵列的相邻单元的方法，装置和系统，以确定相邻单元的阈值电压值，相邻单元与目标单元相邻，以及读取存储器的目标单元 阵列使用基于相邻单元的阈值电压值的字线电压值。 描述了附加装置，系统和方法。

公开(公告)号：US09508440B2

公开(公告)日：2016-11-29

申请号：US14688149

申请日：2015-04-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seiichi Aritome

IPC: G11C11/34 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/102 ,  G11C16/26

Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

公开(公告)号：US09070450B2

公开(公告)日：2015-06-30

申请号：US14099530

申请日：2013-12-06

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome

IPC: G11C16/04 ,  G11C16/06 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/06 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.

Abstract translation: 本公开包括用于操作非易失性多电平存储器单元的方法，设备，模块和系统。 一种方法实施例包括向耦合到行选择线的第一单元分配可以对第一单元编程的第一数量的编程状态。 该方法包括将耦合到行选择线的第二单元分配给可编程第二单元的第二数量的编程状态，其中第二数量的编程状态大于第一数量的编程状态。 该方法包括在将第二单元编程到第二数量的编程状态之前将第一单元编程为第一数量的编程状态之一。

公开(公告)号：US09030874B2

公开(公告)日：2015-05-12

申请号：US14150568

申请日：2014-01-08

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome

IPC: G11C16/04 ,  G11C16/16 ,  H01L27/02 ,  H01L27/115

CPC classification number: G11C16/0483 ,  G11C16/16 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: A system and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. One such method includes applying a first voltage level to a first edge word line of a memory block string and applying a second voltage level to a second edge word line of the memory block string. Such a method might also include applying a third voltage level to non-edge word lines of the memory block string.

Abstract translation: 一种用于调整例如浮动存储器阵列等存储器阵列中的阈值编程和擦除电压的系统和装置。 一种这样的方法包括将第一电压电平施加到存储器块串的第一边缘字线并将第二电压电平施加到存储器块串的第二边缘字线。 这种方法还可以包括将第三电压电平施加到存储器块串的非边缘字线。

公开(公告)号：US09018059B2

公开(公告)日：2015-04-28

申请号：US13866698

申请日：2013-04-19

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/115

CPC classification number: H01L21/762 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.

Abstract translation: 一种存储器阵列，包括相对于彼此具有隔离的栅极间电介质区域的晶体管。 晶体管被形成为使得阵列中的每个晶体管具有电荷存储区域，例如浮置栅极，控制栅极和栅极之间的介电层。 每个晶体管的栅极间电介质层与阵列中的每个其它晶体管的栅极间电介质隔离。