Invention Grant
US09018976B2 Dual-port positive level sensitive reset preset data retention latch
有权
双端口正电平敏感复位预置数据保持锁存器
- Patent Title: Dual-port positive level sensitive reset preset data retention latch
- Patent Title (中): 双端口正电平敏感复位预置数据保持锁存器
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Application No.: US14080183Application Date: 2013-11-14
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Publication No.: US09018976B2Publication Date: 2015-04-28
- Inventor: Steven C. Bartling , Sudhanshu Khanna
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Frank D. Cimino
- Main IPC: H03K19/173
- IPC: H03K19/173

Abstract:
In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.
Public/Granted literature
- US20150054545A1 DUAL-PORT POSITIVE LEVEL SENSITIVE RESET PRESET DATA RETENTION LATCH Public/Granted day:2015-02-26
Information query
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