Invention Grant
US09021320B2 pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains
有权
具有在不同电压域中工作的多个异步子芯片的pBIST架构
- Patent Title: pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains
- Patent Title (中): 具有在不同电压域中工作的多个异步子芯片的pBIST架构
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Application No.: US13709168Application Date: 2012-12-10
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Publication No.: US09021320B2Publication Date: 2015-04-28
- Inventor: Raguram Damodaran , Naveen Bhoria , Aman Kokrady
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/12 ; G11C5/14 ; G11C29/16 ; G11C29/04
Abstract:
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.
Public/Granted literature
- US20140164854A1 pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING IN DIFFERRING VOLTAGE DOMAINS Public/Granted day:2014-06-12
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