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公开(公告)号：US12093690B2
公开(公告)日：2024-09-17
申请号：US17952517
申请日：2022-09-26
IPC分类号： G06F9/30 , G06F9/38 , G06F9/445 , G06F12/02 , G06F16/31 , G06F16/41 , G06F16/901 , G11C11/409 , G06F3/06 , G06F9/355 , G06F12/0811
CPC分类号： G06F9/30145 , G06F9/30007 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30101 , G06F9/30105 , G06F9/3818 , G06F9/44505 , G06F12/0246 , G06F12/0292 , G06F16/322 , G06F16/41 , G06F16/9017 , G11C11/409 , G06F3/0647 , G06F9/30167 , G06F9/355 , G06F12/0811
摘要： A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.
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公开(公告)号：US12086064B2
公开(公告)日：2024-09-10
申请号：US17847131
申请日：2022-06-22
发明人： Abhijeet Ashok Chachad , Timothy David Anderson , Pramod Kumar Swami , Naveen Bhoria , David Matthew Thompson , Neelima Muralidharan
IPC分类号： G06F12/08 , G06F12/0811 , G06F12/10
CPC分类号： G06F12/0811 , G06F12/10 , G06F2212/608
摘要： An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.
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公开(公告)号：US11960891B2
公开(公告)日：2024-04-16
申请号：US17686584
申请日：2022-03-04
IPC分类号： G06F9/30 , G06F9/38 , G06F9/445 , G06F12/02 , G06F16/31 , G06F16/41 , G06F16/901 , G11C11/409 , G06F3/06 , G06F9/355 , G06F12/0811
CPC分类号： G06F9/30145 , G06F9/30007 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30101 , G06F9/30105 , G06F9/3818 , G06F9/44505 , G06F12/0246 , G06F12/0292 , G06F16/322 , G06F16/41 , G06F16/9017 , G11C11/409 , G06F3/0647 , G06F9/30167 , G06F9/355 , G06F12/0811
摘要： A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.
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公开(公告)号：US20240095164A1
公开(公告)日：2024-03-21
申请号：US17945242
申请日：2022-09-15
IPC分类号： G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/603
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.
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公开(公告)号：US20240028523A1
公开(公告)日：2024-01-25
申请号：US18477674
申请日：2023-09-29
IPC分类号： G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126 , G06F12/127
CPC分类号： G06F12/128 , G06F12/0888 , G06F12/0891 , G06F9/546 , G06F12/0215 , G06F12/0238 , G06F12/0811 , G06F12/082 , G06F12/0804 , G06F9/3001 , G06F9/30047 , G11C7/106 , G11C7/1087 , G11C29/42 , G11C29/44 , G06F11/1064 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/1605 , G06F12/121 , G06F12/0292 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/222 , G11C7/1075 , G11C7/1078 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G11C5/066 , G11C7/10 , G11C7/1015 , G06F15/8069 , G06F12/0802 , G06F9/30043 , G06F12/126 , G06F12/127 , G06F2212/1021 , G06F2212/608 , G06F2212/6032 , G06F2212/1024 , G06F2212/62 , G06F2212/1016 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6042
摘要： Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.
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公开(公告)号：US11803486B2
公开(公告)日：2023-10-31
申请号：US17842257
申请日：2022-06-16
IPC分类号： G06F12/0895 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126
CPC分类号： G06F12/0895 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/082 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/6042 , G06F2212/62
摘要： A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.
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公开(公告)号：US20230333991A1
公开(公告)日：2023-10-19
申请号：US18337104
申请日：2023-06-19
IPC分类号： G06F12/126 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
CPC分类号： G06F12/126 , G06F12/0888 , G06F12/0891 , G06F9/546 , G06F12/0215 , G06F12/0238 , G06F12/0811 , G06F12/128 , G06F12/082 , G06F12/0804 , G06F9/3001 , G06F9/30047 , G11C7/106 , G11C7/1087 , G11C29/42 , G11C29/44 , G06F11/1064 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/1605 , G06F12/121 , G06F12/0292 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/222 , G11C7/1075 , G11C7/1078 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G11C5/066 , G11C7/10 , G11C7/1015 , G06F15/8069 , G06F12/0802 , G06F9/30043 , G06F2212/1021 , G06F2212/608 , G06F2212/6032 , G06F2212/1024 , G06F2212/62 , G06F2212/1016 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6042
摘要： Methods, apparatus, systems and articles of manufacture to facilitate write miss caching in cache system are disclosed. An example apparatus includes a first cache storage; a second cache storage, wherein the second cache storage includes a first portion operable to store a first set of data evicted from the first cache storage and a second portion; a cache controller coupled to the first cache storage and the second cache storage and operable to: receive a write operation; determine that the write operation produces a miss in the first cache storage; and in response to the miss in the first cache storage, provide write miss information associated with the write operation to the second cache storage for storing in the second portion.
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公开(公告)号：US11789868B2
公开(公告)日：2023-10-17
申请号：US17498921
申请日：2021-10-12
IPC分类号： G06F12/0811 , G06F12/0815 , G06F12/128 , G06F12/0817 , G06F12/084 , G06F9/30 , G06F11/30 , G06F12/0808 , G06F13/16 , G06F9/38 , G06F9/46 , G06F9/54 , G06F12/0895 , G06F12/0831
CPC分类号： G06F12/0811 , G06F9/30047 , G06F9/30079 , G06F9/3867 , G06F9/467 , G06F9/544 , G06F9/546 , G06F11/3037 , G06F12/084 , G06F12/0808 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0895 , G06F12/128 , G06F13/1668 , G06F2212/1021 , G06F2212/608
摘要： An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.
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公开(公告)号：US11741020B2
公开(公告)日：2023-08-29
申请号：US16882238
申请日：2020-05-22
IPC分类号： G06F12/08 , G06F12/00 , G11C7/10 , G06F12/0811 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/082 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/6042 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding. An example apparatus includes a first storage, a second storage, a store queue coupled to the first storage and the second storage, the store queue operable to receive a first memory operation specifying a first set of data, process the first memory operation for storing the first set of data in at least one of the first storage and the second storage, receive a second memory operation, and prior to storing the first set of data in the at least one of the first storage and the second storage, feedback the first set of data for use in the second memory operation.
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10.发明授权公开(公告)号：US11507513B2
公开(公告)日：2022-11-22
申请号：US16882268
申请日：2020-05-22
IPC分类号： G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed. An example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.
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