Invention Grant
US09025693B2 On-chip interferers for standards compliant jitter tolerance testing
有权
用于符合标准的抖动容限测试的片上干扰源
- Patent Title: On-chip interferers for standards compliant jitter tolerance testing
- Patent Title (中): 用于符合标准的抖动容限测试的片上干扰源
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Application No.: US13538871Application Date: 2012-06-29
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Publication No.: US09025693B2Publication Date: 2015-05-05
- Inventor: John Wang , Vasudevan Parthasarathy
- Applicant: John Wang , Vasudevan Parthasarathy
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H04B17/00
- IPC: H04B17/00

Abstract:
Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.
Public/Granted literature
- US20130301691A1 On-Chip Interferers for Standards Compliant Jitter Tolerance Testing Public/Granted day:2013-11-14
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