Invention Grant
US09025693B2 On-chip interferers for standards compliant jitter tolerance testing 有权
用于符合标准的抖动容限测试的片上干扰源

On-chip interferers for standards compliant jitter tolerance testing
Abstract:
Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.
Information query
Patent Agency Ranking
0/0