公开(公告)号：US08111738B2

公开(公告)日：2012-02-07

申请号：US12881108

申请日：2010-09-13

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38 ,  H04L7/00 ,  H04L23/00

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US07593457B2

公开(公告)日：2009-09-22

申请号：US10813363

申请日：2004-03-31

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38 ,  H04L7/00

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US20080049847A1

公开(公告)日：2008-02-28

申请号：US11837278

申请日：2007-08-10

Applicant: Vivek Telang ,  Vasudevan Parthasarathy ,  Sudeep Bhoja ,  Hong Chen ,  Afshin Momtaz ,  Chung-Jue Chen ,  Ali Ghiasi ,  Michael Furlong ,  Lorenzo Longo

Inventor： Vivek Telang ,  Vasudevan Parthasarathy ,  Sudeep Bhoja ,  Hong Chen ,  Afshin Momtaz ,  Chung-Jue Chen ,  Ali Ghiasi ,  Michael Furlong ,  Lorenzo Longo

IPC: H04B14/04

CPC classification number: H04L25/03063 ,  H04B10/25133 ,  H04B10/697 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0307 ,  H04L2025/03356 ,  H04L2025/0349 ,  H04L2025/03509

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

公开(公告)号：US20050188284A1

公开(公告)日：2005-08-25

申请号：US10767729

申请日：2004-01-30

Applicant: Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

Inventor： Jay Proano ,  Howard Baumer ,  Chung-Jue Chen ,  Ali Ghiasi ,  Vasudevan Parthasarathy ,  Rajesh Satapathy ,  Linda Ying

IPC: G06F11/00

CPC classification number: H04L43/022 ,  H04L43/0811 ,  H04L43/0823 ,  H04L43/16

Abstract: A method is presented that monitors the quality of a communications channel. The method includes receiving a data signal and establishing a zero reference phase of the received data signal. The method further includes generating a phase-shifted data signal by phase shifting the received data signal relative to the zero reference phase, and sampling the phase-shifted data signal for one or more phase-shift positions. A zero reference phase is reestablished between sampling at each of the phase-shift positions. The method also includes detecting bit errors in the phase-shifted data signal at each of the phase-shift positions in order to provide a communications channel quality measurement. In an embodiment, the method includes generating an eye diagram according to a count of detected bit errors relative to a count of detected bits. The eye diagram characterizes the quality of the communications channel.

Abstract translation: 提出了一种监测通信信道质量的方法。 该方法包括接收数据信号并建立接收数据信号的零参考相位。 该方法还包括通过相对于零参考相位相移所接收的数据信号来产生相移数据信号，并对一个或多个相移位置的相移数据信号进行采样。 在每个相移位置的采样之间重新建立零参考相位。 该方法还包括检测每个相移位置处的相移数据信号中的位错误，以提供通信信道质量测量。 在一个实施例中，该方法包括根据检测到的比特错误的计数相对于检测到的比特的计数来生成眼图。 眼图描绘了通信信道的质量。

公开(公告)号：US20050094734A1

公开(公告)日：2005-05-05

申请号：US10694945

申请日：2003-10-29

Applicant: Vasudevan Parthasarathy

Inventor： Vasudevan Parthasarathy

IPC: H04B3/00

CPC classification number: H04L25/0272 ,  H04L25/02 ,  H04L25/0292

Abstract: An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken. However, if the received data word is invalid, then the parallel differential signal is inverted using a logic circuit, which will correct the error if it is due to cross-connection of the differential lines at the interface or anywhere else.

Abstract translation: 在通信系统中实现自动极性交换。 具有差分输入和输出的两个或多个收发器通过诸如背板的接口耦合在一起以形成通信系统。 在这种配置中，可以将接口处的差分数据线或信号交叉连接，这将导致在第二收发器处接收的无效数据字。 因此，本发明包括在并行到串行转换之后检测无效数据字的错误检查和校正模块。 更具体地，错误检查确定并行差分信号是否表示有效的数据字。 这可以通过例如存储和比较诸如RAM的存储器中的有效数据字来完成。 如果接收到的数据字有效，则不采取任何纠正措施。 然而，如果接收到的数据字无效，则使用逻辑电路对并行差分信号进行反相，如果由于差分线在接口或其他任何地方的交叉连接，则将纠正错误。

公开(公告)号：US09025693B2

公开(公告)日：2015-05-05

申请号：US13538871

申请日：2012-06-29

Applicant: John Wang ,  Vasudevan Parthasarathy

Inventor： John Wang ,  Vasudevan Parthasarathy

IPC: H04B17/00

CPC classification number: H04B17/14

Abstract: Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.

Abstract translation: 提供了便于片上测试的系统和方法。 集成电路可以包括被配置为经由通信信道发送通信信号的发射机。 集成电路还可以包括被配置为经由通信信道接收通信信号的接收机。 抖动创建模块还可以形成集成电路的一部分，并且可以将抖动引入系统，从而允许进行片上抖动测试。 抖动创建模块可以形成发射机或接收机的一部分，并且可以通过相位插值来引入抖动。

公开(公告)号：US20110191657A1

公开(公告)日：2011-08-04

申请号：US13014511

申请日：2011-01-26

Applicant: William BLISS ,  Vasudevan Parthasarathy

Inventor： William BLISS ,  Vasudevan Parthasarathy

IPC: H03M13/07 ,  G06F11/10

CPC classification number: H03M13/151 ,  H03M13/05 ,  H03M13/1515 ,  H04B7/0456 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/03949 ,  H04L25/4917 ,  H04L27/00 ,  H04L27/02

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract translation: 在传统的背板以太网系统中，使用PAM-2方案和10.3125 GHz的波特率，通过两对铜线路在一个方向上传输数据，给出10.3125 Gbps的有效比特率。 在背板以太网系统中数据传输的速率仍然可靠地接收，通常受到铜迹线色散性质引起的ISI的限制，主要由皮肤效应引起的频率依赖传输损耗和铜迹线的介电损耗 ，以及相邻通信线路的串扰。 本发明涉及用于克服这些和其他信号损伤的系统，以实现高达和超过与背板以太网系统相关联的常规10Gbps限制的两倍的速度。

公开(公告)号：US20110191656A1

公开(公告)日：2011-08-04

申请号：US13014519

申请日：2011-01-26

Applicant: William BLISS ,  Vasudevan PARTHASARATHY

Inventor： William BLISS ,  Vasudevan PARTHASARATHY

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/151 ,  H03M13/05 ,  H03M13/1515 ,  H04B7/0456 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/03949 ,  H04L25/4917 ,  H04L27/00 ,  H04L27/02

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract translation: 在传统的背板以太网系统中，使用PAM-2方案和10.3125 GHz的波特率，通过两对铜线路在一个方向上传输数据，给出10.3125 Gbps的有效比特率。 在背板以太网系统中数据传输的速率仍然可靠地接收，通常受到铜迹线色散性质引起的ISI的限制，主要由皮肤效应引起的频率依赖传输损耗和铜迹线的介电损耗 ，以及相邻通信线路的串扰。 本发明涉及用于克服这些和其他信号损伤的系统，以实现高达和超过与背板以太网系统相关联的常规10Gbps限制的两倍的速度。

公开(公告)号：US20110007785A1

公开(公告)日：2011-01-13

申请号：US12881108

申请日：2010-09-13

Applicant: Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

Inventor： Abbas Amirichimeh ,  Howard Baumer ,  John Louie ,  Vasudevan Parthasarathy ,  Linda Ying

IPC: H04B1/38

CPC classification number: H03K5/135 ,  H04L7/0012 ,  H04L7/0091

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract translation: 公开了一种收发器系统，其包括多个收发器芯片。 每个收发器芯片包括一个或多个SERDES内核。 每个SERDES核心包​​括一个或多个SERDES通道。 每个SERDES通道包括接收通道和发送通道。 每个SERDES通道的发送通道与相应的接收通道锁相。 收发器系统具有将发送部件的发送时钟信号相位锁定在接收部件的接收时钟信号相位的能力，该接收时钟信号相位是不同SERDES通道的一部分的接收时钟信号相位，不同的SERDES内核，不同的基板，甚至是 一个不同的董事会。 每个SERDES核心接收和传输连接到SERDES核心的外部组件（例如硬盘驱动器）的数据。 还公开了将数据从耦合到接收信道的第一外部组件传送到耦合到发射信道的第二外部组件的方法。

公开(公告)号：US07830987B2

公开(公告)日：2010-11-09

申请号：US11837301

申请日：2007-08-10

Applicant: Sudeep Bhoja ,  Vasudevan Parthasarathy ,  Vivek Telang

Inventor： Sudeep Bhoja ,  Vasudevan Parthasarathy ,  Vivek Telang

IPC: H04L27/14

CPC classification number: H04L7/0062

Abstract: Embodiments include a system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel. The system may include a channel identification module configured to receive a first digitized version of the information bearing signal and an equalized version of the information-bearing signal, and may be configured to determine an impulse response of the communication channel based thereon. The system may include a time varying phase detector configured to receive the equalized version of the information bearing signal, a second digitized version of the information-bearing signal, and the impulse response, and may be further configured to generate a reference wave based on the impulse response and the equalized version of the information-bearing signal. The time varying phase detector may be configured to generate a phase signal based on the reference wave and on an error signal determined from the reference wave and the second digitized version of the information-bearing signal.

Abstract translation: 实施例包括用于对通过通信信道发送的信息承载信号执行电子色散补偿的系统。 系统可以包括信道识别模块，其被配置为接收信息承载信号的第一数字化版本和信息承载信号的均衡版本，并且可以被配置为基于该信道识别模块来确定通信信道的脉冲响应。 系统可以包括时变相位检测器，其被配置为接收信息承载信号的均衡版本，信息承载信号的第二数字化版本和脉冲​​响应，并且还可以被配置为基于 脉冲响应和信息承载信号的均衡版本。 时变相位检测器可以被配置为基于参考波和从信息承载信号的参考波和第二数字化版本确定的误差信号来生成相位信号。