Invention Grant
- Patent Title: Bond pad stack for transistors
- Patent Title (中): 晶体管的焊盘堆叠
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Application No.: US14334738Application Date: 2014-07-18
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Publication No.: US09030023B2Publication Date: 2015-05-12
- Inventor: Jing Wang , Lin Lin , Qiuling Jia , Qi Yang , Jianxin Liu
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank Cimino
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/522 ; H01L29/78 ; H01L23/495

Abstract:
A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.
Public/Granted literature
- US20150008511A1 BOND PAD STACK FOR TRANSISTORS Public/Granted day:2015-01-08
Information query
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