公开(公告)号：US20180061828A1

公开(公告)日：2018-03-01

申请号：US15790212

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L27/088 ,  H01L29/94 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L49/02 ,  H01L27/06 ,  H01L23/528 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US09461131B1

公开(公告)日：2016-10-04

申请号：US14739230

申请日：2015-06-15

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L21/336 ,  H01L27/108 ,  H01L29/423 ,  H01L27/088 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

Abstract translation: 一种集成电路，其包括在衬底中的沟槽，其具有在沟槽的侧壁和底部上生长的高质量沟槽氧化物，其中形成在侧壁上的高质量沟槽氧化物的厚度与形成在底部上的厚度之比较小 超过1.2。 包括具有高质量氧化物的沟槽的集成电路通过首先在1050℃至1250℃的温度范围内在稀释氧中生长牺牲氧化物而形成，剥离牺牲氧化物，在稀释氧中生长高质量的氧化物 在1050℃至1250℃的温度下加入反式1,2-二氯乙烯，并在1050℃至1250℃的温度范围内在惰性环境中退火高品质氧化物。

公开(公告)号：US09030023B2

公开(公告)日：2015-05-12

申请号：US14334738

申请日：2014-07-18

Applicant: Texas Instruments Incorporated

Inventor： Jing Wang ,  Lin Lin ,  Qiuling Jia ,  Qi Yang ,  Jianxin Liu

IPC: H01L23/00 ,  H01L23/522 ,  H01L29/78 ,  H01L23/495

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/522 ,  H01L24/03 ,  H01L24/73 ,  H01L29/7802 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2224/05144

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract translation: 一种用于在半导体管芯上形成接合焊盘的方法包括形成包括底部和顶部电介质层的电介质层，所述电介质层具有穿过其的接触孔穿过接合焊盘。 接触孔内的底部电介质层的外边缘延伸超过顶部电介质层的外边缘以限定接合焊盘边缘。 沉积第一金属层上的第二金属层。 仅在接触孔内形成第一光致抗蚀剂层。 湿蚀刻第二金属层，以将第二金属层从接触孔中的底部电介质层的侧壁凹陷。 仅在接触孔内形成第二光致抗蚀剂层。 第一金属层被湿蚀刻以从顶部介电层凹入第一金属层。 第一金属层在接合焊盘边缘上延伸到底部介电层上。

公开(公告)号：US08815730B1

公开(公告)日：2014-08-26

申请号：US13934956

申请日：2013-07-03

Applicant: Texas Instruments Incorporated

Inventor： Jing Wang ,  Lin Lin ,  Qiuling Jia ,  Qi Yang ,  Jianxin Liu

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/522 ,  H01L24/03 ,  H01L24/73 ,  H01L29/7802 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/32245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2224/05144

Abstract: A method for forming bond pads on a semiconductor die includes forming a dielectric stack including a bottom and top dielectric layer having a contact hole therethrough over a bond pad. An outer edge of the bottom dielectric layer within the contact hole extends beyond an outer edge of the top dielectric layer to define a bond pad edge. A second metal layer on a first metal layer is deposited. A first photoresist layer is formed exclusively within the contact hole. The second metal layer is wet etched to recess the second metal layer from sidewalls of the bottom dielectric layer in the contact hole. A second photoresist layer is formed exclusively within the contact hole. The first metal layer is wet etched to recess the first metal layer from the top dielectric layer. The first metal layer extends over the bond pad edge onto the bottom dielectric layer.

Abstract translation: 一种用于在半导体管芯上形成接合焊盘的方法包括形成包括底部和顶部电介质层的电介质层，所述电介质层具有穿过其的接触孔穿过接合焊盘。 接触孔内的底部电介质层的外边缘延伸超过顶部电介质层的外边缘以限定接合焊盘边缘。 沉积第一金属层上的第二金属层。 仅在接触孔内形成第一光致抗蚀剂层。 湿蚀刻第二金属层，以将第二金属层从接触孔中的底部电介质层的侧壁凹陷。 仅在接触孔内形成第二光致抗蚀剂层。 第一金属层被湿蚀刻以从顶部介电层凹入第一金属层。 第一金属层在接合焊盘边缘上延伸到底部介电层上。

公开(公告)号：US10347626B2

公开(公告)日：2019-07-09

申请号：US15790212

申请日：2017-10-23

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L23/528 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.

公开(公告)号：US09825030B2

公开(公告)日：2017-11-21

申请号：US15255311

申请日：2016-09-02

Applicant: Texas Instruments Incorporated

Inventor： Yufei Xiong ,  Yunlong Liu ,  Hong Yang ,  Jianxin Liu

IPC: H01L27/108 ,  H01L27/088 ,  H01L29/423 ,  H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/28 ,  H01L29/66 ,  H01L29/94 ,  H01L23/528 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L27/088 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66181 ,  H01L29/7827 ,  H01L29/945

Abstract: An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio of the thickness of the high quality trench oxide formed on the sidewalls to the thickness formed on the bottom is less than 1.2. An integrated circuit including a trench with high quality oxide is formed by first growing a sacrificial oxide in dilute oxygen at a temperature in the range of 1050° C. to 1250° C., stripping the sacrificial oxide, growing high quality oxide in dilute oxygen plus trans 1,2 dichloroethylene at a temperature in the range of 1050° C. to 1250° C., and annealing the high quality oxide in an inert ambient at a temperature in the range of 1050° C. to 1250° C.