Invention Grant
- Patent Title: Semiconductor package and method of manufacturing the same
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US13688823Application Date: 2012-11-29
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Publication No.: US09041182B2Publication Date: 2015-05-26
- Inventor: Toshihiko Nagano , Kazuhide Abe , Hiroshi Yamada , Kazuhiko Itaya , Taihei Nakada
- Applicant: Toshihiko Nagano , Kazuhide Abe , Hiroshi Yamada , Kazuhiko Itaya , Taihei Nakada
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-075518 20120329
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/78 ; H01L23/055 ; H01L23/10 ; H01L23/00 ; H01L23/66
Abstract:
A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.
Public/Granted literature
- US20130256864A1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2013-10-03
Information query
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