Invention Grant
- Patent Title: Multi-threaded system for performing atomic binary translations
- Patent Title (中): 用于执行原子二进制翻译的多线程系统
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Application No.: US14088446Application Date: 2013-11-25
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Publication No.: US09053035B1Publication Date: 2015-06-09
- Inventor: Ashish Mathur , Sandeep Jain
- Applicant: Ashish Mathur , Sandeep Jain
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G06F12/08

Abstract:
A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.
Public/Granted literature
- US20150149725A1 MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS Public/Granted day:2015-05-28
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