Invention Grant
US09053923B2 Methods for fabricating integrated circuits including topographical features for directed self-assembly
有权
用于制造集成电路的方法，包括用于定向自组装的形貌特征
- Patent Title: Methods for fabricating integrated circuits including topographical features for directed self-assembly
- Patent Title (中): 用于制造集成电路的方法，包括用于定向自组装的形貌特征
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Application No.: US14072149Application Date: 2013-11-05
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Publication No.: US09053923B2Publication Date: 2015-06-09
- Inventor: Azat Latypov , Edward Teoh Kah Ching , He Yi
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/02 ; H01L21/306 ; H01L21/308 ; H01L21/027
Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well.
Public/Granted literature
- US20150126034A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING TOPOGRAPHICAL FEATURES FOR DIRECTED SELF-ASSEMBLY Public/Granted day:2015-05-07
Information query
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