Invention Grant
US09059686B2 Pseudo-CML latch and divider having reduced charge sharing between output nodes
有权
伪CML锁存器和分压器具有降低的输出节点之间的电荷共享
- Patent Title: Pseudo-CML latch and divider having reduced charge sharing between output nodes
- Patent Title (中): 伪CML锁存器和分压器具有降低的输出节点之间的电荷共享
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Application No.: US13926680Application Date: 2013-06-25
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Publication No.: US09059686B2Publication Date: 2015-06-16
- Inventor: Wu-Hsin Chen , Li Liu , Jianyun Hu
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox LLP
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03K3/027 ; H03K3/037 ; H03K3/017 ; H01L21/8238 ; H03K3/356

Abstract:
In one example, a high-speed divider includes two identical pseudo-CML latches and four output inverters. Each latch includes a pair of cross-coupled signal holding transistors. A first P-channel pull-up circuit pulls up on a second output node QB of the latch. A second P-channel pull-up circuit pulls up on a first output node Q of the latch. A pull-down circuit involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.
Public/Granted literature
- US20140375367A1 PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES Public/Granted day:2014-12-25
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