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US09064935B2 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry 有权
在集成电路的制造中形成多条导线的方法，形成导线阵列的方法和集成电路

  • 专利标题： Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry
  • 专利标题（中）： 在集成电路的制造中形成多条导线的方法，形成导线阵列的方法和集成电路
  • 申请号： US13182293
    申请日： 2011-07-13
  • 公开(公告)号： US09064935B2
    公开(公告)日： 2015-06-23
  • 发明人: Sanh Tang , Ming Zhang
  • 申请人： Sanh Tang , Ming Zhang
  • 申请人地址： US ID Boise
  • 专利权人： Micron Technology, Inc.
  • 当前专利权人： Micron Technology, Inc.
  • 当前专利权人地址： US ID Boise
  • 代理机构： Wells St. John, P.S.
  • 主分类号： H01L23/48
  • IPC分类号： H01L23/48 ;  H01L21/768
Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of forming an array of conductive lines, and integrated circuitry
摘要：
A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.
摘要（中）：

在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。 导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。 导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。 蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。 考虑其他实现。

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