公开(公告)号：US07989336B2

公开(公告)日：2011-08-02

申请号：US12436262

申请日：2009-05-06

申请人： Sanh Tang ,  Ming Zhang

发明人： Sanh Tang ,  Ming Zhang

IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76877 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.

摘要翻译： 在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。 导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。 导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。 蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。 考虑其他实现。

公开(公告)号：US20100283155A1

公开(公告)日：2010-11-11

申请号：US12436262

申请日：2009-05-06

申请人： Sanh Tang ,  Ming Zhang

发明人： Sanh Tang ,  Ming Zhang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.

摘要翻译： 在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。 导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。 导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。 蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。 考虑其他实现。

公开(公告)号：US09064935B2

公开(公告)日：2015-06-23

申请号：US13182293

申请日：2011-07-13

申请人： Sanh Tang ,  Ming Zhang

发明人： Sanh Tang ,  Ming Zhang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.

摘要翻译： 在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。 导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。 导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。 蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。 考虑其他实现。

公开(公告)号：US20110266689A1

公开(公告)日：2011-11-03

申请号：US13182293

申请日：2011-07-13

申请人： Sanh Tang ,  Ming Zhang

发明人： Sanh Tang ,  Ming Zhang

IPC分类号： H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/7682 ,  H01L21/76838 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated.

摘要翻译： 在集成电路的制造中形成一对导线的方法包括将沟槽形成为接纳在衬底上的镶嵌材料。 导电材料沉积在镶嵌材料上并且在沟槽内沉积以覆盖沟槽。 导电材料至少被去除到镶嵌材料，以留下留在沟槽中的至少一些导电材料。 蚀刻通过沟槽内的导电材料纵向导电，以在沟槽内形成第一和第二导电线，该沟槽中的第一和第二导电线沿着第一和第二导电线的至少大部分长度在横截面上相互镜像。 考虑其他实现。

公开(公告)号：US20070141771A1

公开(公告)日：2007-06-21

申请号：US11704487

申请日：2007-02-09

申请人： Sanh Tang ,  Gordon Haller

发明人： Sanh Tang ,  Gordon Haller

IPC分类号： H01L21/8238

CPC分类号： H01L29/0653 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

公开(公告)号：US20070020819A1

公开(公告)日：2007-01-25

申请号：US11495473

申请日：2006-07-28

申请人： Sanh Tang ,  Grant Huglin

发明人： Sanh Tang ,  Grant Huglin

IPC分类号： H01L21/332 ,  H01L21/84 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/42392 ,  H01L29/66666 ,  H01L29/7827

摘要： The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.

公开(公告)号：US20060261393A1

公开(公告)日：2006-11-23

申请号：US11496930

申请日：2006-07-31

申请人： Sanh Tang ,  Gordon Haller ,  Kris Brown ,  Tuman Earl Allen

发明人： Sanh Tang ,  Gordon Haller ,  Kris Brown ,  Tuman Earl Allen

IPC分类号： H01L29/94

CPC分类号： H01L29/41758 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/78

摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

公开(公告)号：US20060205128A1

公开(公告)日：2006-09-14

申请号：US11076774

申请日：2005-03-10

申请人： Sanh Tang ,  Gordon Haller

发明人： Sanh Tang ,  Gordon Haller

IPC分类号： H01L21/8234 ,  H01L21/76 ,  H01L21/20

CPC分类号： H01L29/0653 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

摘要翻译： 公开了形成场效应晶体管的集成电路和方法。 在一个方面，集成电路包括包括本体半导体材料的半导体衬底。 电绝缘材料容纳在本体半导体材料内。 在绝缘材料上形成半导体材料。 包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。 在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。 在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。 公开了其他方面和实施方式，包括方法方面。

公开(公告)号：US20060043471A1

公开(公告)日：2006-03-02

申请号：US10928522

申请日：2004-08-26

申请人： Sanh Tang ,  Grant Huglin

发明人： Sanh Tang ,  Grant Huglin

IPC分类号： H01L29/76

CPC分类号： H01L29/42392 ,  H01L29/66666 ,  H01L29/7827

摘要： The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.

摘要翻译： 本发明包括通过定义具有自对准特征的垂直环绕栅极场效应晶体管的沟道长度而形成的垂直晶体管。 该方法提供了定义晶体管沟道长度的工艺步骤和用于形成用于制造半导体器件的垂直周围栅极场效应晶体管结构的凹槽硅柱。

公开(公告)号：US20060043449A1

公开(公告)日：2006-03-02

申请号：US10932150

申请日：2004-09-01

申请人： Sanh Tang ,  Gordon Haller ,  Kris Brown ,  Tuman Allen

发明人： Sanh Tang ,  Gordon Haller ,  Kris Brown ,  Tuman Allen

IPC分类号： H01L29/94

CPC分类号： H01L29/41758 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/78

摘要： The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

摘要翻译： 本发明包括具有上表面的半导体衬底的晶体管器件。 一对源极/漏极区域形成在半导体衬底内，并且沟道区形成在半导体衬底内并相对于半导体衬底的上表面大致垂直地延伸。 栅极形成在半导体衬底中的一对源/漏区之间。