Invention Grant
- Patent Title: Logic circuit
- Patent Title (中): 逻辑电路
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Application No.: US13761302Application Date: 2013-02-07
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Publication No.: US09083334B2Publication Date: 2015-07-14
- Inventor: Jun Koyama , Kengo Akimoto , Masashi Tsubuku
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office, P.C.
- Agent Eric J. Robinson
- Priority: JP2008-281647 20081031
- Main IPC: H03K19/20
- IPC: H03K19/20 ; H03K19/094 ; H01L27/12 ; H03K19/096 ; H01L27/088

Abstract:
An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
Public/Granted literature
- US20130147519A1 LOGIC CIRCUIT Public/Granted day:2013-06-13
Information query
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