Invention Grant
US09087784B2 Structure and method of Tinv scaling for high k metal gate technology
有权
用于高k金属栅极技术的Tinv缩放的结构和方法
- Patent Title: Structure and method of Tinv scaling for high k metal gate technology
- Patent Title (中): 用于高k金属栅极技术的Tinv缩放的结构和方法
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Application No.: US14167532Application Date: 2014-01-29
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Publication No.: US09087784B2Publication Date: 2015-07-21
- Inventor: Michael P. Chudzik , Dechao Guo , Siddarth A. Krishnan , Unoh Kwon , Carl J. Radens , Shahab Siddiqui
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/8238 ; H01L27/092
Abstract:
A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.
Public/Granted literature
- US20140170844A1 STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY Public/Granted day:2014-06-19
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