Invention Grant
- Patent Title: Stack of semiconductor structures and corresponding manufacturing method
- Patent Title (中): 堆叠半导体结构及相应的制造方法
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Application No.: US14519832Application Date: 2014-10-21
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Publication No.: US09093456B2Publication Date: 2015-07-28
- Inventor: Laurent-Luc Chapelon
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles Cedex
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles Cedex
- Agency: Gardere Wynne Sewell LLP
- Priority: FR1254157 20120507
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/768 ; H01L23/498 ; H01L25/065 ; H01L23/538 ; H01L23/48 ; H01L25/00 ; H01L25/07 ; H01L21/56 ; H01L23/00 ; H01L21/683

Abstract:
A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
Public/Granted literature
- US20150054140A1 STACK OF SEMICONDUCTOR STRUCTURES AND CORRESPONDING MANUFACTURING METHOD Public/Granted day:2015-02-26
Information query
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