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公开(公告)号：US20240332324A1
公开(公告)日：2024-10-03
申请号：US18739927
申请日：2024-06-11
发明人： Francois ROY
IPC分类号： H01L27/146 , H04N25/53 , H04N25/621 , H04N25/705 , H04N25/75 , H04N25/77
CPC分类号： H01L27/14603 , H01L27/1463 , H04N25/53 , H04N25/621 , H04N25/705 , H04N25/75 , H04N25/77
摘要： A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.
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2.发明公开公开(公告)号：US20240274552A1
公开(公告)日：2024-08-15
申请号：US18625631
申请日：2024-04-03
发明人： Didier DUTARTRE
IPC分类号： H01L23/66 , H01L21/762 , H01L29/06
CPC分类号： H01L23/66 , H01L21/76286 , H01L29/0646 , H01L29/0649 , H01L2223/6688
摘要： An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
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公开(公告)号：US20240186090A1
公开(公告)日：2024-06-06
申请号：US18193230
申请日：2023-03-30
申请人： STMICROELECTRONICS SA , STMicroelectronics (Crolles 2) SAS , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Philippe CATHELIN , Frederic GIANESELLO , Alain FLEURY , Stephane MONFRAY , Bruno REIG , Vincent PUYAL
CPC分类号： H01H37/34 , H10N70/231 , H10N70/826 , H10N70/8413 , H10N70/882
摘要： The present description concerns a switch based on a phase-change material comprising: first, second, and third electrodes; a first region of said phase-change material coupling the first and second electrodes; and —a second region of said phase-change material coupling the second and third electrodes.
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公开(公告)号：US20240176129A1
公开(公告)日：2024-05-30
申请号：US18193223
申请日：2023-03-30
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics (Crolles 2) SAS
发明人： Sandrine VILLENAVE , Quentin ABADIE
CPC分类号： G02B26/001 , G01J3/26 , G02B5/28
摘要： The present description concerns an optical filter intended to be arranged in front of an image sensor comprising a plurality of pixels, the filter comprising, for each pixel, at least one resonant cavity comprising a transparent region having a first refraction index and laterally delimited by a reflective peripheral vertical wall, and at least one resonant element formed in said region.
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公开(公告)号：US11984360B2
公开(公告)日：2024-05-14
申请号：US17728088
申请日：2022-04-25
IPC分类号： H01L21/82 , H01L21/3105 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L29/66 , H01L29/737 , H01L29/93
CPC分类号： H01L21/8222 , H01L21/31056 , H01L21/8249 , H01L27/0664 , H01L29/66174 , H01L29/66242 , H01L29/7371 , H01L29/93
摘要： A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.
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6.发明公开公开(公告)号：US20240153557A1
公开(公告)日：2024-05-09
申请号：US18535335
申请日：2023-12-11
申请人： Universite D'Aix Marseille , Centre National de la Recherche Scientifique , STMicroelectronics (Crolles 2) SAS
发明人： Jean-Michel PORTAL , Vincenzo DELLA MARCA , Jean-Pierre WALDER , Julien GASQUEZ , Philippe BOIVIN
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2013/0054 , G11C2213/72
摘要： A method for operating a sense amplifier in a one-switch one-resistance (1S1R) memory array, includes: generating a regulated full voltage and a regulated half voltage; applying the regulated full voltage and regulated half voltage to selected and unselected bit lines of the 1S1R memory array during read operations as an applied read voltage; and inducing and compensating for a sneak-path current during read operations by adjusting the applied read voltage based on the cell state of an accessed bit cell and an amplitude of the sneak-path current.
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公开(公告)号：US11957067B2
公开(公告)日：2024-04-09
申请号：US17328917
申请日：2021-05-24
发明人： Philippe Boivin , Simon Jeannot
CPC分类号： H10N70/231 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/061 , H10N70/253 , H10N70/823 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/8828 , G11C13/0004 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US11955481B2
公开(公告)日：2024-04-09
申请号：US17992602
申请日：2022-11-22
IPC分类号： H01L27/08 , H01L21/8228 , H01L27/082
CPC分类号： H01L27/0826 , H01L21/82285
摘要： A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.
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公开(公告)号：US20240105730A1
公开(公告)日：2024-03-28
申请号：US18532984
申请日：2023-12-07
发明人： Olivier WEBER , Christophe LECOCQ
IPC分类号： H01L27/12 , H01L21/8238 , H01L21/84 , H01L27/02 , H01L27/092
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/0207 , H01L27/092
摘要： An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.
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10.发明授权公开(公告)号：US11901278B2
公开(公告)日：2024-02-13
申请号：US18095629
申请日：2023-01-11
IPC分类号： H01L23/495 , H01L23/498 , H01L21/48 , H01L31/02
CPC分类号： H01L23/49822 , H01L21/4857 , H01L23/49894 , H01L31/02016
摘要： A first circuit structure of an electronic IC device includes comprises light-sensitive optical circuit components. A second circuit structure of the electronic IC device includes an electronic circuit component and an electrically-conductive layer extending between and at a distance from the optical circuit components and the electronic circuit component. Electrical connections link the optical circuit components and the electronic circuit component. These electrical connections are formed in holes which pass through dielectric layers and the intermediate conductive layer. Electrical insulation rings between the electrical connections and the conductive layer are provided which surround the electrical connections and have a thickness equal to a thickness of the conductive layer.
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