Invention Grant
- Patent Title: High voltage CMOS with triple gate oxide
- Patent Title (中): 具有三栅极氧化物的高电压CMOS
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Application No.: US13663015Application Date: 2012-10-29
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Publication No.: US09117687B2Publication Date: 2015-08-25
- Inventor: Binghua Hu , Pinghai Hao , Sameer Pendharkar , Seetharaman Sridhar , Jarvis Jacobs
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/06 ; H01L21/761 ; H01L29/78 ; H01L29/10 ; H01L29/423 ; H01L29/45 ; H01L29/49 ; H01L29/66
Abstract:
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
Public/Granted literature
- US20130105909A1 HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE Public/Granted day:2013-05-02
Information query
IPC分类:
