Invention Grant
US09117754B2 Methods for extending floating gates for NVM cells to form sub-lithographic features and related NVM cells
有权
扩展NVM单元浮动栅格以形成亚光刻特征和相关NVM单元的方法
- Patent Title: Methods for extending floating gates for NVM cells to form sub-lithographic features and related NVM cells
- Patent Title (中): 扩展NVM单元浮动栅格以形成亚光刻特征和相关NVM单元的方法
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Application No.: US14168093Application Date: 2014-01-30
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Publication No.: US09117754B2Publication Date: 2015-08-25
- Inventor: Anirban Roy , Craig A. Cavins
- Applicant: Anirban Roy , Craig A. Cavins
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Egan, Peterman & Enders LLP.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/28 ; H01L29/49 ; H01L29/423 ; H01L29/66 ; H01L27/112

Abstract:
Methods are disclosed for extending floating gate regions within floating gate cells to form sub-lithographic features. Related floating gate cells and non-volatile memory (NVM) systems are also disclosed. In part, the disclosed embodiments utilize a spacer etch to form extended floating gate regions and floating gate slits with sub-lithographic dimensions thereby achieving desired increased spacing between control gate layers and doped regions underlying floating gate structures while still allowing for reductions in the overall size of floating-gate NVM cells. These advantageous results are achieved in part by depositing an additional floating gate layer over previously formed floating gate regions and then using the spacer etch to form the extended floating gate regions as sidewall structures and sub-lithographic floating gate slits. The resulting floating gate structures reduce breakdown down risks, thereby improving device reliability.
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