Invention Grant
- Patent Title: Synchronizing a translation lookaside buffer with an extended paging table
- Patent Title (中): 将翻译后备缓冲区与扩展分页表同步
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Application No.: US14517849Application Date: 2014-10-18
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Publication No.: US09122624B2Publication Date: 2015-09-01
- Inventor: Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Mnemoglyphics, LLC
- Agent Lawrence M. Mennemeier
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/10

Abstract:
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
Public/Granted literature
- US20150039850A1 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE Public/Granted day:2015-02-05
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