Invention Grant
- Patent Title: 3D memory process and structures
- Patent Title (中): 3D内存过程和结构
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Application No.: US13914539Application Date: 2013-06-10
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Publication No.: US09123579B2Publication Date: 2015-09-01
- Inventor: Erh-Kun Lai , Chia-Jung Chiu , Chieh Lo
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW
- Agency: Baker & McKenzie LLP
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L27/105

Abstract:
A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.
Public/Granted literature
- US20140264615A1 3D MEMORY PROCESS AND STRUCTURES Public/Granted day:2014-09-18
Information query
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